l4 and g4 are the same, g4 just has some extra registers, and the first
section is the same for wb as well, all of them had missing reserved
registers.

Have some demo code using lptim, lpuart, exti and rtc mostly working.
It glitches into undefined exceptions, so it's a little concerning,
but... it's all cross checked against RM0440_rev7, so it's pretty good.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>

FIXME: LPTIM should be split out, rcc should squish to earlier, as early
as we can with other rcc fixes,post the last dev_v2 merge.

Some people might like to turn peripherals back off again.  We have all
the machinery in place, so make it easy for them.

Signed-off-by: Karl Palsson <karlp@etactica.com>

Includes the f4, l0 and wb.  f4 renames MEMRM to MEMRMP to be both
consistent with other parts and consistent with ref man.

Retested on the WB, but l0 and f4 code was simply moved.
For yaml files, given how varied syscfg is, we default to using the
family name as the type, but still allow overriding via explicit type in
the yaml file if desired.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>

While checking STM32WB, this was easy enough to just transcribe while
working.  Untested on real hardware.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>

Max speed on WB is 32MHz HSE to 64MHz PLL.  Must ensure that CPU2
doesn't exceed 32MHz though.
Adds the remaining RCC registers and bits as well.  Most of these are not
useful, as you can't really/meaningfully deliver software to CPU2, but
some of them are used/required by the ST provided WPAN middleware.

Signed-off-by: Karl Palsson <karlp@etactica.com>
Signed-off-by: Karl Palsson <karlp@tweak.net.au>

By flipping the name/number definition, we can define aliases such as
ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have
code that both matches reference manuals, and also code that matches
between lines.

runtime tested on WB, compile tested on F3.
Signed-off-by: Karl Palsson <karlp@etactica.com>