diff options
| author | Karl Palsson <karlp@etactica.com> | 2021-09-14 17:29:14 +0200 |
|---|---|---|
| committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2021-09-16 20:29:55 +0200 |
| commit | 4d56457b6939d35307880e41bd6a42fe1799e125 (patch) | |
| tree | 322a9ed1c291d8bf89b41759a6ab26278d50768e | |
| parent | 996cf482bcf49fd58ab84eddd2ad9b138bcc425b (diff) | |
platforms: add stm32wb
Basic RCC and memory map support.
Signed-off-by: Karl Palsson <karlp@etactica.com>
| -rw-r--r-- | platforms/stm32/index.yaml | 4 | ||||
| -rw-r--r-- | platforms/stm32/wb.yaml | 161 | ||||
| -rw-r--r-- | rcc/rcc_reg.h | 46 |
3 files changed, 211 insertions, 0 deletions
diff --git a/platforms/stm32/index.yaml b/platforms/stm32/index.yaml index ca234bd..3eeee06 100644 --- a/platforms/stm32/index.yaml +++ b/platforms/stm32/index.yaml @@ -9,3 +9,7 @@ - match: family: f7 -: !import f7.yaml + + - match: + family: wb + -: !import wb.yaml diff --git a/platforms/stm32/wb.yaml b/platforms/stm32/wb.yaml new file mode 100644 index 0000000..4277085 --- /dev/null +++ b/platforms/stm32/wb.yaml @@ -0,0 +1,161 @@ +- match: + mem: c + mem: + flash: + origin: 0x08000000 + size: 256k + +- match: + mem: e + mem: + flash: + origin: 0x08000000 + size: 512k + +- match: + mem: g + mem: + flash: + origin: 0x08000000 + size: 1M + +- mem: + ram: + origin: 0x20000000 + size: 192k + ram_shared: + origin: 0x20030000 + size: 10k + + periph: + stm32_uart: + USART1: + type: v2 + offset: 0x40013800 + + rcc: + RCC: + offset: 0x58000000 + type: wb + bus: + AHB1: + 0: DMA1 + 1: DMA2 + 2: DMAMUX1 + 12: CRC + 16: TSC + + AHB2: + 0: GPIOA + 1: GPIOB + 2: GPIOC + 3: GPIOD + 4: GPIOE + 7: GPIOH + 13: ADC1 + + AHB3: + 8: QUADSPI + 16: PKA + 17: AES2 + 18: RNG + 19: HSEM + 20: IPCC + 25: FLASH + 7: OTGFS + + APB1: + 0: TIM2 + 9: LCD + 10: RTCAPB + 11: WWDG + 14: SPI2 + 21: I2C1 + 23: I2C3 + 24: CRS + 26: USB + 31: LPTIM1 + + APB1_2: + 0: LPUART1 + 5: LPTIM2 + + APB2: + 11: TIM1 + 12: SPI1 + 14: USART1 + 17: TIM16 + 18: TIM17 + 21: SAI1 + + interrupt: + irq: + 0: WWDG + 1: PVD + 2: TAMP_STAMP + 3: RTC_WKUP + 4: FLASH + 5: RCC + 6: EXTI0 + 7: EXTI1 + 8: EXTI2 + 9: EXTI3 + 10: EXTI4 + 11: DMA1_CH1 + 12: DMA1_CH2 + 13: DMA1_CH3 + 14: DMA1_CH4 + 15: DMA1_CH5 + 16: DMA1_CH6 + 17: DMA1_CH7 + 18: ADC1 + 19: USB_HP + 20: USB_LP + 21: C2SEV + 22: COMP + 23: EXTI9_5 + 24: TIM1_BRK + 25: TIM1_UP_TIM16 + 26: TIM1_TRG_COM_TIM17 + 27: TIM1_CC + 28: TIM2 + 29: PKA + 30: I2C1_EV + 31: I2C1_ER + 32: I2C3_EV + 33: I2C3_ER + 34: SPI1 + 35: SPI2 + 36: USART1 + 37: LPUART1 + 38: SAI1 + 39: TSC + 40: EXTI15_10 + 41: RTC_Alarm + 42: CRS_IT + 43: SOTF_BLEACT_802ACT_RFPHASE + 44: IPCC_C1_RX + 45: IPCC_C1_TX + 46: HSEM + 47: LPTIM1 + 48: LPTIM2 + 49: LCD + 50: QUADSPI + 51: AES1 + 52: AES2 + 53: TRNG + 54: FPU + 55: DMA2_CH1 + 56: DMA2_CH2 + 57: DMA2_CH3 + 58: DMA2_CH4 + 59: DMA2_CH5 + 60: DMA2_CH6 + 61: DMA2_CH7 + 62: DMAMUX1_OVR + + define: + - STM32WB + + meta: + cpu: cortex-m4f diff --git a/rcc/rcc_reg.h b/rcc/rcc_reg.h index f9f3735..7130015 100644 --- a/rcc/rcc_reg.h +++ b/rcc/rcc_reg.h @@ -111,6 +111,52 @@ struct RCC_reg_l0_t { volatile uint32_t CSR; }; +struct RCC_reg_wb_t { + volatile uint32_t CR; + volatile uint32_t ICSCR; + volatile uint32_t CFGR; + volatile uint32_t PLLCFGR; + volatile uint32_t PLLSAI1CFGR; + volatile uint32_t _1; // reserved 0x14 + volatile uint32_t CIER; + volatile uint32_t CIFR; + volatile uint32_t CICR; + volatile uint32_t SMPSCR; + volatile uint32_t AHB1RSTR; + volatile uint32_t AHB2RSTR; + volatile uint32_t AHB3RSTR; + volatile uint32_t _2; // reserved 0x34 + volatile uint32_t APB1RSTR1; + volatile uint32_t APB1RSTR2; + volatile uint32_t APB2RSTR; + volatile uint32_t APB3RSTR; + volatile uint32_t AHB1ENR; + volatile uint32_t AHB2ENR; + volatile uint32_t AHB3ENR; + volatile uint32_t _3; // reserved 0x54 + volatile uint32_t APB1ENR1; + volatile uint32_t APB1ENR2; + volatile uint32_t APB2ENR; + volatile uint32_t _4; // reserved 0x64 + volatile uint32_t AHB1SMENR; + volatile uint32_t AHB2SMENR; + volatile uint32_t AHB3SMENR; + volatile uint32_t _5; // reserved 0x74 + volatile uint32_t APB1SMENR1; + volatile uint32_t APB1SMENR2; + volatile uint32_t APB2SMENR; + volatile uint32_t _6; // reserved 0x84 + volatile uint32_t CCIPR; + volatile uint32_t _7; // reserved 0x8c + volatile uint32_t BDCR; + volatile uint32_t CSR; + volatile uint32_t CRRCR; + volatile uint32_t HSECR; + // FIXME: reserved 0xa0-0x104, then EXTCFGR + // FIXME: reserved 0x10c-0x144, then C2xxxx starts +}; + + template <typename T> class RCC_t : public mmio_ptr<T> { public: |