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| author | Karl Palsson <karlp@tweak.net.au> | 2022-01-31 01:17:52 +0100 |
|---|---|---|
| committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2022-04-16 21:37:28 +0200 |
| commit | 7fb9f96855c43867a5a9451c431a42d37e0f3539 (patch) | |
| tree | 66d00f86a78a5876c2dc2b727487cb0b8e798a6e | |
| parent | 9fe219dde499f88ab6314bfc879b8fbef875386f (diff) | |
FIXME: platforms: stm32l4: fix all rcc enables, add lptim
FIXME: LPTIM should be split out, rcc should squish to earlier, as early
as we can with other rcc fixes,post the last dev_v2 merge.
| -rw-r--r-- | platforms/stm32/l4.yaml | 23 | ||||
| -rw-r--r-- | rcc/rcc_reg.h | 44 | ||||
| -rw-r--r-- | uart/stm32_uart.h | 13 |
3 files changed, 78 insertions, 2 deletions
diff --git a/platforms/stm32/l4.yaml b/platforms/stm32/l4.yaml index bc5f873..33322d9 100644 --- a/platforms/stm32/l4.yaml +++ b/platforms/stm32/l4.yaml @@ -78,6 +78,11 @@ offset: 0x40002800 backup_count: 32 + stm32_syscfg: + SYSCFG: + type: wb # Yes, wb has a couple of extras, but otherwise same. + offset: 0x40010000 + stm32_timer: TIM1: offset: 0x40012C00 @@ -114,7 +119,7 @@ type: v2 offset: 0x40004c00 LPUART1: - type: FIXME + type: lpv1 offset: 0x40008000 rcc: @@ -128,6 +133,7 @@ FLASH: 8 CRC: 12 TSC: 16 + DMA2D: 17 AHB2: GPIOA: 0 @@ -135,17 +141,25 @@ GPIOC: 2 GPIOD: 3 GPIOE: 4 + GPIOF: 5 + GPIOG: 6 GPIOH: 7 + OTGFS: 12 ADC1: 13 + DCMI: 14 AES1: 16 + HASH: 17 RNG1: 18 AHB3: + FMC: 0 QUADSPI: 8 APB1_1: TIM2: 0 TIM3: 1 + TIM4: 2 + TIM5: 3 TIM6: 4 TIM7: 5 LCD: 9 @@ -155,12 +169,14 @@ SPI3: 15 USART2: 17 USART3: 18 - UART3: 19 + UART4: 19 + UART5: 20 I2C1: 21 I2C2: 22 I2C3: 23 CRS: 24 CAN1: 25 + CAN2: 26 USB: 26 PWR: 28 DAC1: 29 @@ -179,10 +195,13 @@ SDMMC1: 10 TIM1: 11 SPI1: 12 + TIM8: 13 USART1: 14 TIM15: 16 TIM16: 17 + TIM17: 18 SAI1: 21 + SAI2: 22 DFSDM1: 24 interrupt: diff --git a/rcc/rcc_reg.h b/rcc/rcc_reg.h index 7663739..1223362 100644 --- a/rcc/rcc_reg.h +++ b/rcc/rcc_reg.h @@ -132,6 +132,50 @@ struct RCC_reg_l1_t { volatile uint32_t CSR; }; +struct RCC_reg_l4_t { + volatile uint32_t CR; + volatile uint32_t ICSCR; + volatile uint32_t CFGR; + volatile uint32_t PLLCFGR; + volatile uint32_t PLLSAI1CFGR; + volatile uint32_t PLLSAI2CFGR; + volatile uint32_t CIER; + volatile uint32_t CIFR; + volatile uint32_t CICR; + uint32_t _1; // reserved 0x24 + volatile uint32_t AHB1RSTR; + volatile uint32_t AHB2RSTR; + volatile uint32_t AHB3RSTR; + uint32_t _2; // reserved 0x34 + volatile uint32_t APB1RSTR1; + volatile uint32_t APB1RSTR2; + volatile uint32_t APB2RSTR; + volatile uint32_t APB3RSTR; + volatile uint32_t AHB1ENR; + volatile uint32_t AHB2ENR; + volatile uint32_t AHB3ENR; + uint32_t _3; // reserved 0x54 + volatile uint32_t APB1ENR1; + volatile uint32_t APB1ENR2; + volatile uint32_t APB2ENR; + uint32_t _4; // reserved 0x64 + volatile uint32_t AHB1SMENR; + volatile uint32_t AHB2SMENR; + volatile uint32_t AHB3SMENR; + uint32_t _5; // reserved 0x74 + volatile uint32_t APB1SMENR1; + volatile uint32_t APB1SMENR2; + volatile uint32_t APB2SMENR; + uint32_t _6; // reserved 0x84 + volatile uint32_t CCIPR; + uint32_t _7; // reserved 0x8c + volatile uint32_t BDCR; + volatile uint32_t CSR; + volatile uint32_t CRRCR; + volatile uint32_t CCIPR2; +}; + + struct RCC_reg_wb_t { volatile uint32_t CR; volatile uint32_t ICSCR; diff --git a/uart/stm32_uart.h b/uart/stm32_uart.h index 4c2a09d..08f93d1 100644 --- a/uart/stm32_uart.h +++ b/uart/stm32_uart.h @@ -27,6 +27,19 @@ struct STM32_UART_reg_v2_t { volatile uint32_t PRESC; // Gx, L4+, Wx etc }; +struct STM32_UART_reg_lpv1_t { + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t CR3; + volatile uint32_t BRR; + uint32_t _1[2]; + volatile uint32_t RQR; + volatile uint32_t ISR; + volatile uint32_t ICR; + volatile uint32_t RDR; + volatile uint32_t TDR; +}; + template <typename T> class STM32_UART_t : public mmio_ptr<T> { public: |