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| author | Vegard Storheil Eriksen <zyp@jvnv.net> | 2022-09-10 20:19:37 +0200 |
|---|---|---|
| committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2022-09-10 20:22:27 +0200 |
| commit | d60be6f83a4519afc0875f28f0959c51edb4fbeb (patch) | |
| tree | d2aafc4d027e879b2de103056aee5d53ddef28ab | |
| parent | 23a2994e051488561294050993f16162f24a85e7 (diff) | |
riscv: Add rv32ima and rv32im.
| -rw-r--r-- | platforms/riscv.yaml | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/platforms/riscv.yaml b/platforms/riscv.yaml index f66a3ef..5764af2 100644 --- a/platforms/riscv.yaml +++ b/platforms/riscv.yaml @@ -4,8 +4,24 @@ cflags: - -march=rv32imac - -mabi=ilp32 - - -msmall-data-limit=0 + +- match: + cpu: rv32ima + cflags: + - -march=rv32ima + - -mabi=ilp32 + +- match: + cpu: rv32im + + cflags: + - -march=rv32im + - -mabi=ilp32 + +- cflags: + - -msmall-data-limit=0 + interrupt: exception: 0: InstructionMisaligned |