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authorKarl Palsson <karlp@etactica.com>2021-09-15 17:05:36 +0200
committerVegard Storheil Eriksen <zyp@jvnv.net>2021-09-16 20:29:55 +0200
commit891344a7f602e9431a52b89d32d3b5a8e2b0430c (patch)
tree6a125fe4a059b7806d089b5f63531679434f0e56 /dma
parentd68a78807e7708c480b2fc9d34e1873714423aae (diff)
dma: convert to new style, add DMAMUX
DMAMUX is a channel/source muxer available on L4+,L5,H7,G0,G4,WB and WL parts. Signed-of-by: Karl Palsson <karlp@etactica.com>
Diffstat (limited to 'dma')
-rw-r--r--dma/SConscript29
-rw-r--r--dma/dma.h60
-rw-r--r--dma/stm32_dma.h43
-rw-r--r--dma/stm32_dmamux.h30
4 files changed, 102 insertions, 60 deletions
diff --git a/dma/SConscript b/dma/SConscript
new file mode 100644
index 0000000..2ee2444
--- /dev/null
+++ b/dma/SConscript
@@ -0,0 +1,29 @@
+Import('env')
+
+headers = []
+instances = []
+sources = []
+aliases = {}
+
+periph = env['PLATFORM_SPEC'].get('periph', {})
+
+if 'stm32_dmamux' in periph:
+ headers.append('stm32_dmamux.h')
+ for name, data in periph['stm32_dmamux'].items():
+ instances.append({
+ 'type': 'STM32_DMAMUX_t<STM32_DMAMUX_reg_%s_t>' % data['type'],
+ 'name': name,
+ 'args': [data['offset']],
+ })
+if 'stm32_dma' in periph:
+ headers.append('stm32_dma.h')
+ for name, data in periph['stm32_dma'].items():
+ instances.append({
+ 'type': 'STM32_DMA_t<STM32_DMA_reg_%s_t>' % data['type'],
+ 'name': name,
+ 'args': [data['offset']],
+ })
+env.Jinja2('dma.h', '../templates/periph_instances.h.j2', headers = headers, instances = instances, aliases = aliases)
+
+
+Return('sources') \ No newline at end of file
diff --git a/dma/dma.h b/dma/dma.h
deleted file mode 100644
index 4d9b8d6..0000000
--- a/dma/dma.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef DMA_H
-#define DMA_H
-
-#include <stdint.h>
-
-#if defined(STM32F3)
-struct DMA_channel_reg_t {
- volatile uint32_t CR;
- volatile uint32_t NDTR;
- volatile uint32_t PAR;
- volatile uint32_t MAR;
- uint32_t _reserved;
-};
-
-struct DMA_reg_t {
- volatile uint32_t ISR;
- volatile uint32_t IFCR;
- DMA_channel_reg_t C[7];
-};
-
-class DMA_t {
- public:
- DMA_reg_t& reg;
-
- DMA_t(uint32_t reg_addr) : reg(*(DMA_reg_t*)reg_addr) {}
-};
-
-static DMA_t DMA1(0x40020000);
-static DMA_t DMA2(0x40020400);
-
-#elif defined(STM32F4)
-struct DMA_stream_reg_t {
- volatile uint32_t CR;
- volatile uint32_t NDTR;
- volatile uint32_t PAR;
- volatile uint32_t M0AR;
- volatile uint32_t M1AR;
- volatile uint32_t FCR;
-};
-
-struct DMA_reg_t {
- volatile uint32_t LISR;
- volatile uint32_t HISR;
- volatile uint32_t LIFCR;
- volatile uint32_t HIFCR;
- DMA_stream_reg_t S[8];
-};
-
-class DMA_t {
- public:
- DMA_reg_t& reg;
-
- DMA_t(uint32_t reg_addr) : reg(*(DMA_reg_t*)reg_addr) {}
-};
-
-static DMA_t DMA1(0x40026000);
-static DMA_t DMA2(0x40026400);
-#endif
-
-#endif
diff --git a/dma/stm32_dma.h b/dma/stm32_dma.h
new file mode 100644
index 0000000..afeaed5
--- /dev/null
+++ b/dma/stm32_dma.h
@@ -0,0 +1,43 @@
+#pragma once
+
+#include <stdint.h>
+#include <mmio/mmio.h>
+
+struct STM32_DMA_channel_reg_v1_t {
+ volatile uint32_t CR;
+ volatile uint32_t NDTR;
+ volatile uint32_t PAR;
+ volatile uint32_t MAR;
+ uint32_t _reserved;
+};
+
+struct STM32_DMA_reg_v1_t {
+ volatile uint32_t ISR;
+ volatile uint32_t IFCR;
+ STM32_DMA_channel_reg_v1_t C[7];
+};
+
+
+struct STM32_DMA_stream_reg_v2_t {
+ volatile uint32_t CR;
+ volatile uint32_t NDTR;
+ volatile uint32_t PAR;
+ volatile uint32_t M0AR;
+ volatile uint32_t M1AR;
+ volatile uint32_t FCR;
+};
+
+struct STM32_DMA_reg_v2_t {
+ volatile uint32_t LISR;
+ volatile uint32_t HISR;
+ volatile uint32_t LIFCR;
+ volatile uint32_t HIFCR;
+ STM32_DMA_stream_reg_v2_t S[8];
+};
+
+
+template <typename T>
+class STM32_DMA_t : public mmio_ptr<T> {
+ public:
+ using mmio_ptr<T>::ptr;
+};
diff --git a/dma/stm32_dmamux.h b/dma/stm32_dmamux.h
new file mode 100644
index 0000000..064393a
--- /dev/null
+++ b/dma/stm32_dmamux.h
@@ -0,0 +1,30 @@
+#pragma once
+
+#include <stdint.h>
+#include <mmio/mmio.h>
+
+struct STM32_DMAMUX_reg_v1_t {
+ /**
+ * Not all parts offer all channels!
+ * WB: 14, G4: 16...
+ */
+ volatile uint32_t CCR[20];
+ volatile uint32_t _reserved1[12];
+ volatile uint32_t CSR; // 0x80
+ volatile uint32_t CFR; // 0x84
+ volatile uint32_t _reserved2[30];
+ /**
+ * Not all parts offer all requests!
+ * WB/G4: 4, H7: 8
+ */
+ volatile uint32_t RGCR[8]; // 0x100
+ volatile uint32_t _reserved3[8];
+ volatile uint32_t RGSR; // 0x140
+ volatile uint32_t RGCFR;
+};
+
+template <typename T>
+class STM32_DMAMUX_t : public mmio_ptr<T> {
+ public:
+ using mmio_ptr<T>::ptr;
+}; \ No newline at end of file