stm32wb: exti: initial registers

Basic registers to start with, a lot of commonality, but extra registers
on the WB.

Signed-off-by <karlp@tweak.net.au>

2 files changed, 54 insertions, 0 deletions

diff --git a/exti/SConscript b/exti/SConscript
new file mode 100644
index 0000000..b620818
--- /dev/null
+++ b/exti/SConscript
@@ -0,0 +1,21 @@
+Import('env')
+
+headers = []
+instances = []
+sources = []
+aliases = {}
+
+periph = env['PLATFORM_SPEC'].get('periph', {})
+
+if 'stm32_exti' in periph:
+    headers.append('stm32_exti.h')
+    for name, data in periph['stm32_exti'].items():
+        instances.append({
+            'type': 'STM32_EXTI_t<STM32_EXTI_reg_%s_t>' % data['type'],
+            'name': name,
+            'args': [data['offset']],
+        })
+
+env.Jinja2('exti.h', '../templates/periph_instances.h.j2', headers = headers, instances = instances, aliases = aliases)
+
+Return('sources')
diff --git a/exti/stm32_exti.h b/exti/stm32_exti.h
new file mode 100644
index 0000000..525a483
--- /dev/null
+++ b/exti/stm32_exti.h
@@ -0,0 +1,33 @@
+#pragma once
+
+#include <mmio/mmio.h>
+
+struct STM32_EXTI_reg_wb_t {
+	volatile uint32_t RTSR1;
+	volatile uint32_t FTSR1;
+	volatile uint32_t SWIER1;
+	volatile uint32_t PR1;
+	uint32_t _reserved1[4];
+	volatile uint32_t RTSR2;
+	volatile uint32_t FTSR2;
+	volatile uint32_t SWIER2;
+	volatile uint32_t PR2;
+	uint32_t _reserved2[20];
+	volatile uint32_t IMR1;
+	volatile uint32_t EMR1;
+	uint32_t _reserved3[2];
+	volatile uint32_t IMR2;
+	volatile uint32_t EMR2;
+	uint32_t _reserved4[10];
+	volatile uint32_t C2IMR1;
+	volatile uint32_t C2EMR1;
+	uint32_t _reserved5[2];
+	volatile uint32_t C2IMR2;
+	volatile uint32_t C2EMR2;
+};
+
+template <typename T>
+class STM32_EXTI_t : public mmio_ptr<T> {
+    public:
+        using mmio_ptr<T>::ptr;
+};