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authorVegard Storheil Eriksen <zyp@jvnv.net>2021-09-15 23:16:11 +0200
committerVegard Storheil Eriksen <zyp@jvnv.net>2021-09-15 23:16:11 +0200
commit968937d0d937487ab301f017c145889fc0e94692 (patch)
treea62e27423fdc515c71624def636b63b12f06cf57 /interrupt/dispatch_clic.cpp
parent9194e871a4590d1118f40ea8dbf1d34e45bc759c (diff)
platforms: Add initial RISC-V/GD32V support.
Diffstat (limited to 'interrupt/dispatch_clic.cpp')
-rw-r--r--interrupt/dispatch_clic.cpp25
1 files changed, 25 insertions, 0 deletions
diff --git a/interrupt/dispatch_clic.cpp b/interrupt/dispatch_clic.cpp
new file mode 100644
index 0000000..64e4bfc
--- /dev/null
+++ b/interrupt/dispatch_clic.cpp
@@ -0,0 +1,25 @@
+#include "interrupt.h"
+
+extern interrupt::vector_t vectors_exception[];
+extern interrupt::vector_t vectors_clic[];
+
+[[gnu::interrupt, gnu::aligned(64)]]
+void riscv_interrupt_handler() {
+ uint32_t cause;
+ asm("csrr %0, mcause" : "=r"(cause));
+
+ uint32_t type = cause & 0x80000000;
+ uint32_t code = cause & 0x00000fff;
+
+ if(type) {
+ vectors_clic[code]();
+ } else {
+ vectors_exception[code]();
+ }
+}
+
+[[gnu::constructor(200)]]
+void riscv_interrupt_init() {
+ asm volatile("csrw mtvec, %0" :: "r"(intptr_t(riscv_interrupt_handler) | 3));
+ asm volatile("csrrsi x0, mstatus, (1 << 3)");
+}