diff options
| author | Karl Palsson <karlp@tweak.net.au> | 2022-01-31 01:17:52 +0100 |
|---|---|---|
| committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2022-04-16 21:37:28 +0200 |
| commit | 7fb9f96855c43867a5a9451c431a42d37e0f3539 (patch) | |
| tree | 66d00f86a78a5876c2dc2b727487cb0b8e798a6e /rcc | |
| parent | 9fe219dde499f88ab6314bfc879b8fbef875386f (diff) | |
FIXME: platforms: stm32l4: fix all rcc enables, add lptim
FIXME: LPTIM should be split out, rcc should squish to earlier, as early
as we can with other rcc fixes,post the last dev_v2 merge.
Diffstat (limited to 'rcc')
| -rw-r--r-- | rcc/rcc_reg.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/rcc/rcc_reg.h b/rcc/rcc_reg.h index 7663739..1223362 100644 --- a/rcc/rcc_reg.h +++ b/rcc/rcc_reg.h @@ -132,6 +132,50 @@ struct RCC_reg_l1_t { volatile uint32_t CSR; }; +struct RCC_reg_l4_t { + volatile uint32_t CR; + volatile uint32_t ICSCR; + volatile uint32_t CFGR; + volatile uint32_t PLLCFGR; + volatile uint32_t PLLSAI1CFGR; + volatile uint32_t PLLSAI2CFGR; + volatile uint32_t CIER; + volatile uint32_t CIFR; + volatile uint32_t CICR; + uint32_t _1; // reserved 0x24 + volatile uint32_t AHB1RSTR; + volatile uint32_t AHB2RSTR; + volatile uint32_t AHB3RSTR; + uint32_t _2; // reserved 0x34 + volatile uint32_t APB1RSTR1; + volatile uint32_t APB1RSTR2; + volatile uint32_t APB2RSTR; + volatile uint32_t APB3RSTR; + volatile uint32_t AHB1ENR; + volatile uint32_t AHB2ENR; + volatile uint32_t AHB3ENR; + uint32_t _3; // reserved 0x54 + volatile uint32_t APB1ENR1; + volatile uint32_t APB1ENR2; + volatile uint32_t APB2ENR; + uint32_t _4; // reserved 0x64 + volatile uint32_t AHB1SMENR; + volatile uint32_t AHB2SMENR; + volatile uint32_t AHB3SMENR; + uint32_t _5; // reserved 0x74 + volatile uint32_t APB1SMENR1; + volatile uint32_t APB1SMENR2; + volatile uint32_t APB2SMENR; + uint32_t _6; // reserved 0x84 + volatile uint32_t CCIPR; + uint32_t _7; // reserved 0x8c + volatile uint32_t BDCR; + volatile uint32_t CSR; + volatile uint32_t CRRCR; + volatile uint32_t CCIPR2; +}; + + struct RCC_reg_wb_t { volatile uint32_t CR; volatile uint32_t ICSCR; |