diff options
| author | Karl Palsson <karlp@etactica.com> | 2021-09-17 16:39:47 +0200 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2022-01-20 19:01:51 +0100 |
| commit | 2d8a1c0489da61996bb4787a53353585d0413a03 (patch) | |
| tree | a281cbbd46dd8390657aa8c5ce456b681a6c2377 /rcc | |
| parent | 3da2028a769f03ea3ea4fa1b3d69d0bf19af3b1e (diff) | |
adc: stm32f3: expand and verify
Working with dma and timers. This preserves the somewhat dubious
decision that ADC clock for F1 and F3 should be 12Mhz. It can always be
overridden later.
Diffstat (limited to 'rcc')
| -rw-r--r-- | rcc/rcc.cpp | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/rcc/rcc.cpp b/rcc/rcc.cpp index 25ed29c..794b1ee 100644 --- a/rcc/rcc.cpp +++ b/rcc/rcc.cpp @@ -23,10 +23,14 @@ void rcc_init() { // Set APB1 prescaler to /2. RCC->CFGR |= 0x400; - - // Set ADCCLK prescaler to /6. + + // Set ADCCLK prescaler to /6. => 12MHz is ~sufficient +#if defined(STM32F1) RCC->CFGR |= 0x8000; - +#else + RCC->CFGR2 = (0b10011 << 9) | (0b10011 << 4); +#endif + #elif defined(STM32F4) // Enable HSE. |