diff options
| author | Karl Palsson <karlp@etactica.com> | 2021-09-17 13:14:21 +0200 |
|---|---|---|
| committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2022-01-26 23:40:29 +0100 |
| commit | 3d4618b786594af253a2cf972452e79ae230eccc (patch) | |
| tree | 36aaf3553161d4f199c25d90eaa6d964eca85039 /rcc | |
| parent | d205055dacbb11ee6e7ff6984b69e79cde564686 (diff) | |
rcc: stm32wb: add remaining regs and max speed helper
Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2
doesn't exceed 32MHz though.
Adds the remaining RCC registers and bits as well. Most of these are not
useful, as you can't really/meaningfully deliver software to CPU2, but
some of them are used/required by the ST provided WPAN middleware.
Signed-off-by: Karl Palsson <karlp@etactica.com>
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Diffstat (limited to 'rcc')
| -rw-r--r-- | rcc/rcc.cpp | 26 | ||||
| -rw-r--r-- | rcc/rcc_reg.h | 35 |
2 files changed, 51 insertions, 10 deletions
diff --git a/rcc/rcc.cpp b/rcc/rcc.cpp index 794b1ee..67bb948 100644 --- a/rcc/rcc.cpp +++ b/rcc/rcc.cpp @@ -90,7 +90,31 @@ void rcc_init() { // Select HSI48 for USB. RCC->CCIPR |= 1 << 26; - + + #elif defined(STM32WB) + // Enable HSE. + RCC->CR |= (1<<16); + while(!(RCC->CR & (1<<17))); + + // Configure and enable PLL. + // R=2, Q = 2, P = 2, M = 2, N = 8, src=HSE + const auto m = 2; + const auto n = 8; + const auto p = 2; + const auto q = 2; + const auto r = 2; + + RCC->PLLCFGR = ((r-1)<<29) | (1<<28) | ((q-1)<<25) | ((p-1)<<17) | (n<<8) | ((m-1)<<4) | (3<<0); + RCC->CR |= (1<<24); + while(!(RCC->CR & (1<<25))); + + // 64MHz/2 to keep CPU2 in bounds + RCC->EXTCFGR |= (0b1000 << 4); + + // Switch to PLL. + RCC->CFGR |= 0x3; + while((RCC->CFGR & (3 << 2)) != (3 << 2)); // SWS = PLL + #endif } diff --git a/rcc/rcc_reg.h b/rcc/rcc_reg.h index 7130015..4a1e881 100644 --- a/rcc/rcc_reg.h +++ b/rcc/rcc_reg.h @@ -117,7 +117,7 @@ struct RCC_reg_wb_t { volatile uint32_t CFGR; volatile uint32_t PLLCFGR; volatile uint32_t PLLSAI1CFGR; - volatile uint32_t _1; // reserved 0x14 + uint32_t _1; // reserved 0x14 volatile uint32_t CIER; volatile uint32_t CIFR; volatile uint32_t CICR; @@ -125,7 +125,7 @@ struct RCC_reg_wb_t { volatile uint32_t AHB1RSTR; volatile uint32_t AHB2RSTR; volatile uint32_t AHB3RSTR; - volatile uint32_t _2; // reserved 0x34 + uint32_t _2; // reserved 0x34 volatile uint32_t APB1RSTR1; volatile uint32_t APB1RSTR2; volatile uint32_t APB2RSTR; @@ -133,27 +133,44 @@ struct RCC_reg_wb_t { volatile uint32_t AHB1ENR; volatile uint32_t AHB2ENR; volatile uint32_t AHB3ENR; - volatile uint32_t _3; // reserved 0x54 + uint32_t _3; // reserved 0x54 volatile uint32_t APB1ENR1; volatile uint32_t APB1ENR2; volatile uint32_t APB2ENR; - volatile uint32_t _4; // reserved 0x64 + uint32_t _4; // reserved 0x64 volatile uint32_t AHB1SMENR; volatile uint32_t AHB2SMENR; volatile uint32_t AHB3SMENR; - volatile uint32_t _5; // reserved 0x74 + uint32_t _5; // reserved 0x74 volatile uint32_t APB1SMENR1; volatile uint32_t APB1SMENR2; volatile uint32_t APB2SMENR; - volatile uint32_t _6; // reserved 0x84 + uint32_t _6; // reserved 0x84 volatile uint32_t CCIPR; - volatile uint32_t _7; // reserved 0x8c + uint32_t _7; // reserved 0x8c volatile uint32_t BDCR; volatile uint32_t CSR; volatile uint32_t CRRCR; volatile uint32_t HSECR; - // FIXME: reserved 0xa0-0x104, then EXTCFGR - // FIXME: reserved 0x10c-0x144, then C2xxxx starts + uint32_t _8[26]; + volatile uint32_t EXTCFGR; + uint32_t _9[15]; + volatile uint32_t C2AHB1ENR; + volatile uint32_t C2AHB2ENR; + volatile uint32_t C2AHB3ENR; + uint32_t _10; + volatile uint32_t C2APB1ENR1; + volatile uint32_t C2APB1ENR2; + volatile uint32_t C2APB2ENR; + volatile uint32_t C2APB3ENR; + volatile uint32_t C2AHB1SMENR; + volatile uint32_t C2AHB2SMENR; + volatile uint32_t C2AHB3SMENR; + uint32_t _11; + volatile uint32_t C2APB1SMENR1; + volatile uint32_t C2APB1SMENR2; + volatile uint32_t C2APB2SMENR; + volatile uint32_t C2APB3SMENR; }; |