diff options
| author | Vegard Storheil Eriksen <zyp@jvnv.net> | 2012-11-19 19:11:57 +0100 |
|---|---|---|
| committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2012-11-19 19:11:57 +0100 |
| commit | ac17bb052b9056122dbae6867d4c5252c8eafb47 (patch) | |
| tree | 147c586118903f9df3a4df98f880cc14045ad3f1 /rcc | |
| parent | 2abe655e4b7b49377c6cb43d6959c897866ed4c2 (diff) | |
Added support for F3.
Diffstat (limited to 'rcc')
| -rw-r--r-- | rcc/flash.cpp | 2 | ||||
| -rw-r--r-- | rcc/flash.h | 4 | ||||
| -rw-r--r-- | rcc/rcc.cpp | 2 | ||||
| -rw-r--r-- | rcc/rcc.h | 67 |
4 files changed, 69 insertions, 6 deletions
diff --git a/rcc/flash.cpp b/rcc/flash.cpp index 2b0fb69..528ba57 100644 --- a/rcc/flash.cpp +++ b/rcc/flash.cpp @@ -1,7 +1,7 @@ #include "flash.h" void flash_init() { - #if defined(STM32F1) + #if defined(STM32F1) || defined(STM32F3) // Set flash latency. FLASH.ACR = 0x12; diff --git a/rcc/flash.h b/rcc/flash.h index 30d30a5..abb3484 100644 --- a/rcc/flash.h +++ b/rcc/flash.h @@ -9,7 +9,7 @@ struct FLASH_t { volatile uint32_t OPTKEYR; volatile uint32_t SR; volatile uint32_t CR; - #if defined(STM32F1) + #if defined(STM32F1) || defined(STM32F3) volatile uint32_t AR; volatile uint32_t RESERVED; volatile uint32_t OBR; @@ -19,7 +19,7 @@ struct FLASH_t { #endif }; -#if defined(STM32F1) +#if defined(STM32F1) || defined(STM32F3) static FLASH_t& FLASH = *(FLASH_t*)0x40022000; #elif defined(STM32F4) static FLASH_t& FLASH = *(FLASH_t*)0x40023c00; diff --git a/rcc/rcc.cpp b/rcc/rcc.cpp index 57b8f7d..6028cdc 100644 --- a/rcc/rcc.cpp +++ b/rcc/rcc.cpp @@ -5,7 +5,7 @@ void rcc_init() { // Initialize flash. flash_init(); - #if defined(STM32F1) + #if defined(STM32F1) || defined(STM32F3) // Enable HSE. RCC.CR |= 0x10000; @@ -15,6 +15,20 @@ struct RCC_t { volatile uint32_t APB1ENR; volatile uint32_t BDCR; volatile uint32_t CSR; + #elif defined(STM32F3) + volatile uint32_t CR; + volatile uint32_t CFGR; + volatile uint32_t CIR; + volatile uint32_t APB2RSTR; + volatile uint32_t APB1RSTR; + volatile uint32_t AHBENR; + volatile uint32_t APB2ENR; + volatile uint32_t APB1ENR; + volatile uint32_t BDCR; + volatile uint32_t CSR; + volatile uint32_t AHBRSTR; + volatile uint32_t CFGR2; + volatile uint32_t CFGR3; #elif defined(STM32F4) volatile uint32_t CR; volatile uint32_t PLLCFGR; @@ -109,6 +123,55 @@ struct RCC_t { TIM10 = 1 << 20, TIM11 = 1 << 21 }; + #elif defined(STM32F3) + enum AHB_dev { + DMA1 = 1 << 0, + DMA2 = 1 << 1, + SRAM = 1 << 2, + FLITF = 1 << 4, + CRC = 1 << 6, + GPIOA = 1 << 17, + GPIOB = 1 << 18, + GPIOC = 1 << 19, + GPIOD = 1 << 20, + GPIOE = 1 << 21, + GPIOF = 1 << 22, + TSC = 1 << 24, + ADC12 = 1 << 28, + ADC34 = 1 << 29, + }; + + enum APB1_dev { + TIM2 = 1 << 0, + TIM3 = 1 << 1, + TIM4 = 1 << 2, + TIM6 = 1 << 4, + TIM7 = 1 << 5, + WWDG = 1 << 11, + SPI2 = 1 << 14, + SPI3 = 1 << 15, + USART2 = 1 << 17, + USART3 = 1 << 18, + UART4 = 1 << 19, + UART5 = 1 << 20, + I2C1 = 1 << 21, + I2C2 = 1 << 22, + USB = 1 << 23, + CAN = 1 << 25, + PWR = 1 << 28, + DAC = 1 << 29, + }; + + enum APB2_dev { + SYSCFG = 1 << 0, + TIM1 = 1 << 11, + SPI1 = 1 << 12, + TIM8 = 1 << 13, + USART1 = 1 << 14, + TIM15 = 1 << 16, + TIM16 = 1 << 17, + TIM17 = 1 << 18, + }; #elif defined(STM32F4) enum AHB1_dev { GPIOA = 1 << 0, @@ -181,7 +244,7 @@ struct RCC_t { }; #endif - #if defined(STM32F1) + #if defined(STM32F1) || defined(STM32F3) inline void enable(AHB_dev dev) { AHBENR |= dev; } @@ -207,7 +270,7 @@ struct RCC_t { } }; -#if defined(STM32F1) +#if defined(STM32F1) || defined(STM32F3) static RCC_t& RCC = *(RCC_t*)0x40021000; #elif defined(STM32F4) static RCC_t& RCC = *(RCC_t*)0x40023800; |