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authorKarl Palsson <karlp@tweak.net.au>2022-01-31 01:17:52 +0100
committerVegard Storheil Eriksen <zyp@jvnv.net>2022-04-16 21:37:28 +0200
commit7fb9f96855c43867a5a9451c431a42d37e0f3539 (patch)
tree66d00f86a78a5876c2dc2b727487cb0b8e798a6e /uart
parent9fe219dde499f88ab6314bfc879b8fbef875386f (diff)
FIXME: platforms: stm32l4: fix all rcc enables, add lptim
FIXME: LPTIM should be split out, rcc should squish to earlier, as early as we can with other rcc fixes,post the last dev_v2 merge.
Diffstat (limited to 'uart')
-rw-r--r--uart/stm32_uart.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/uart/stm32_uart.h b/uart/stm32_uart.h
index 4c2a09d..08f93d1 100644
--- a/uart/stm32_uart.h
+++ b/uart/stm32_uart.h
@@ -27,6 +27,19 @@ struct STM32_UART_reg_v2_t {
volatile uint32_t PRESC; // Gx, L4+, Wx etc
};
+struct STM32_UART_reg_lpv1_t {
+ volatile uint32_t CR1;
+ volatile uint32_t CR2;
+ volatile uint32_t CR3;
+ volatile uint32_t BRR;
+ uint32_t _1[2];
+ volatile uint32_t RQR;
+ volatile uint32_t ISR;
+ volatile uint32_t ICR;
+ volatile uint32_t RDR;
+ volatile uint32_t TDR;
+};
+
template <typename T>
class STM32_UART_t : public mmio_ptr<T> {
public: