diff options
| -rw-r--r-- | build_rules | 9 | ||||
| -rw-r--r-- | can/can.h | 2 | ||||
| -rw-r--r-- | ld_scripts/stm32_f04_6.ld | 6 | ||||
| -rw-r--r-- | ld_scripts/stm32_f05_8.ld (renamed from ld_scripts/stm32_f0_8.ld) | 0 | ||||
| -rw-r--r-- | rcc/crs.h | 2 | ||||
| -rw-r--r-- | rcc/flash.cpp | 2 | ||||
| -rw-r--r-- | rcc/flash.h | 4 | ||||
| -rw-r--r-- | rcc/rcc.cpp | 10 | ||||
| -rw-r--r-- | usb/usb.h | 2 |
9 files changed, 29 insertions, 8 deletions
diff --git a/build_rules b/build_rules index d2f15c8..095c8fe 100644 --- a/build_rules +++ b/build_rules @@ -44,13 +44,16 @@ def select_stm32(env, variant): pin_count = variant[9] flash = variant[10] - if family == 'f051': + if family.startswith('f0'): select_arm(env, 'cortex-m0') env.Append(CPPDEFINES = ['STM32F0']) + + sram = family[2] env['LINK_SCRIPT'] = { - '8': 'stm32_f0_8.ld', - }[flash] + ('4', '6'): 'stm32_f04_6.ld', + ('5', '8'): 'stm32_f05_8.ld', + }[sram, flash] elif family == 'f103': select_arm(env, 'cortex-m3') @@ -80,6 +80,8 @@ static CAN_t CAN1(0x40006400, 36000000); #elif defined(STM32F4) static CAN_t CAN1(0x40006400, 42000000); static CAN_t CAN2(0x40006800, 42000000); +#elif defined(STM32F0) +static CAN_t CAN1(0x40006400, 48000000); #endif #endif diff --git a/ld_scripts/stm32_f04_6.ld b/ld_scripts/stm32_f04_6.ld new file mode 100644 index 0000000..f96278d --- /dev/null +++ b/ld_scripts/stm32_f04_6.ld @@ -0,0 +1,6 @@ +MEMORY { + flash (rx) : org = 0x08000000, len = 32k + ram (rwx) : org = 0x20000000, len = 6k +} + +INCLUDE "arm_flash_ram.ld" diff --git a/ld_scripts/stm32_f0_8.ld b/ld_scripts/stm32_f05_8.ld index 289255c..289255c 100644 --- a/ld_scripts/stm32_f0_8.ld +++ b/ld_scripts/stm32_f05_8.ld @@ -21,7 +21,7 @@ class CRS_t { } }; -#if defined(STM32L0) +#if defined(STM32F0) || defined(STM32L0) static CRS_t CRS(0x40006c00); #endif diff --git a/rcc/flash.cpp b/rcc/flash.cpp index 6469b1c..c20b618 100644 --- a/rcc/flash.cpp +++ b/rcc/flash.cpp @@ -13,7 +13,7 @@ void flash_init() { while(FLASH.ACR != 0x105); - #elif defined(STM32L0) + #elif defined(STM32F0) || defined(STM32L0) // SET flash latency. FLASH.ACR = 1 << 0; diff --git a/rcc/flash.h b/rcc/flash.h index c1f7c1c..789c090 100644 --- a/rcc/flash.h +++ b/rcc/flash.h @@ -4,7 +4,7 @@ #include <stdint.h> struct FLASH_t { - #if defined(STM32F1) || defined(STM32F3) + #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) volatile uint32_t ACR; volatile uint32_t KEYR; volatile uint32_t OPTKEYR; @@ -34,7 +34,7 @@ struct FLASH_t { #endif }; -#if defined(STM32F1) || defined(STM32F3) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) static FLASH_t& FLASH = *(FLASH_t*)0x40022000; #elif defined(STM32F4) static FLASH_t& FLASH = *(FLASH_t*)0x40023c00; diff --git a/rcc/rcc.cpp b/rcc/rcc.cpp index aa9147a..65faf33 100644 --- a/rcc/rcc.cpp +++ b/rcc/rcc.cpp @@ -48,6 +48,16 @@ void rcc_init() { // Set APB2 prescaler to /2. RCC.CFGR |= 4 << 13; + #elif defined(STM32F0) + + // Enable HSI48. + RCC.CR2 |= 1 << 16; // HSI48ON + while(!(RCC.CR2 & (1 << 17))); // HSI48RDY + + // Switch to HSI48. + RCC.CFGR |= 3 << 0; // SW = HSI48 + while((RCC.CFGR & (3 << 2)) != (3 << 2)); // SWS = HSI48 + #elif defined(STM32L0) // Enable HSI16. @@ -12,7 +12,7 @@ static F1_USB_t USB(0x40005c00, 0x40006000); static DWC_OTG_t OTG_FS(0x50000000); static DWC_OTG_t OTG_HS(0x40040000); -#elif defined(STM32L0) +#elif defined(STM32F0) || defined(STM32L0) #include "l0_usb.h" static L0_USB_t USB(0x40005c00, 0x40006000); |