| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
|
|
|
|
|
|
Make it a litle easier to read for some bits that are constantly
checked.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
Backup registers are just hardcoded to 32, which is the max seen.
Note that the STM32WB only has 20! I've captured that in the platform
yaml, even though it's not used anywhere (yet?)
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
|
|
Includes the f4, l0 and wb. f4 renames MEMRM to MEMRMP to be both
consistent with other parts and consistent with ref man.
Retested on the WB, but l0 and f4 code was simply moved.
For yaml files, given how varied syscfg is, we default to using the
family name as the type, but still allow overriding via explicit type in
the yaml file if desired.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
Functional, after much hair tearing.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
Accessing Pin.n and Pin.get_portnum() will give you values suitable for
use with EXTI and similar places.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
While checking STM32WB, this was easy enough to just transcribe while
working. Untested on real hardware.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
maybe you're doing something wrong, or maybe you're doing something so
so right. Hand people a salmon and let them make that decision.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
At least the constants to get started.
Note that RM0434r8 says that 0x27 is for revision "B" but rev9 says it's
not revision "X" (Presumably B nomenclature has been dropped?)
|
|
Basic registers to start with, a lot of commonality, but extra registers
on the WB.
Signed-off-by <karlp@tweak.net.au>
|
|
Not sure if "wpan" is the right directory for them, but they didn't feel
like they warranted their own directory each.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
No helpers, just the register map.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
Makes merging and diffing easier later.
|
|
Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2
doesn't exceed 32MHz though.
Adds the remaining RCC registers and bits as well. Most of these are not
useful, as you can't really/meaningfully deliver software to CPU2, but
some of them are used/required by the ST provided WPAN middleware.
Signed-off-by: Karl Palsson <karlp@etactica.com>
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
No API, just pointers to the calibration data and their associated
constants.
|
|
Overload all the things!
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
less end user casting, more back end c++ magic
|
|
Sometimes you really would like to slow things down to get trace out.
|
|
So you don't always have to refer to ADC12 or ADC34
|
|
|
|
By flipping the name/number definition, we can define aliases such as
ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have
code that both matches reference manuals, and also code that matches
between lines.
runtime tested on WB, compile tested on F3.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
At least use print as a function so it can be imported without breaking
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
|
|
Working with dma and timers. This preserves the somewhat dubious
decision that ADC clock for F1 and F3 should be 12Mhz. It can always be
overridden later.
|
|
Sufficient for blinking leds. Not much else tested yet.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
v2 is for everyone except f1, so avoid the yaml spam.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
|
|
ADC has not been converted to new style, so leveraging legacy f3 code
for now.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
This is not hooked up to anything yet, but would be where the GPIOs get
connected if they are converted to new style. There's no reason to pull
this commit by itself though!
|
|
gpio hasn't (yet) been converted to new style.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
Flash hasn't yet been ported to new style.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
"All" parts so far have the v1 timer api, so default to that, but allow
overriding, instead of requiring it to be specified every time.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
Compatible with existing parts, these are extended option and input
selection registers at the end. Found on some Gx, Ux and Wx parts so
far.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
Stub f1 and f3 platform files have been added to preserve the collected
timer base addresses, even though those platforms aren't actually
supported in laks yet.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
DMAMUX is a channel/source muxer available on L4+,L5,H7,G0,G4,WB and WL
parts.
Signed-of-by: Karl Palsson <karlp@etactica.com>
|
|
L4+, G0, G4, WB and the "newer" parts use the usart-v2 registers, but
add a new register at the end. Simply make it available for all v2
implementations.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
same bus.
|
|
Basic RCC and memory map support.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
save that trace bandwidth baby
|
|
Sourced from zyp on irc. Maybe not the best or most permanent name, but
saves dropping it into every project.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
Authors modifying rcc.cpp should add their protos here as desired.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
This makes it easier for end users to see where files have come from.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
Because I can never remember it.
|
|
|
|
|
|
|
|
|
