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2022-09-10stm32g4: Rename DMAMUX1 to DMAMUX.Vegard Storheil Eriksen1-2/+2
2022-09-10build: Add -Wno-volatile to default CXXFLAGS.Vegard Storheil Eriksen1-1/+1
2022-09-10build: Add -fcoroutines to default CXXFLAGS.Vegard Storheil Eriksen1-1/+1
2022-07-28stm32_adc: Rename common blocks to ADC12 and ADC345 respectively.Vegard Storheil Eriksen5-17/+24
2022-07-27stm32g4: Add 512k variant.Vegard Storheil Eriksen1-0/+7
2022-07-27stm32g4: Add ADC.Vegard Storheil Eriksen1-0/+23
2022-07-27adc: convert to new styleKarl Palsson9-58/+120
Converted the old STM32 headers to new style and copied offsets to platform data. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-05-04build: Detect available toolchains.Vegard Storheil Eriksen1-1/+9
2022-04-17stm32_uart: Add more helper functions.Vegard Storheil Eriksen1-12/+38
2022-04-17stm32_uart: Use constraints to make helper functions compatible with all ↵Vegard Storheil Eriksen1-1/+13
versions.
2022-04-16gd32v: invert rcc definitions, add flash/gpioKarl Palsson1-48/+70
inverted RCC definitions came in via: 24507af1a stm32_rcc: allow aliases for enables. Switch the order of definitions for gd32v so it can compile, and enable the f1 gpio and flash peripherals to allow basic compilations to succeed. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16stm32_flash: l4/wb/g4 fix reserved gapsKarl Palsson1-4/+13
l4 and g4 are the same, g4 just has some extra registers, and the first section is the same for wb as well, all of them had missing reserved registers.
2022-04-16WIPWIP: pwr: set lpms_c2?Karl Palsson1-0/+7
really?
2022-04-16stm32g4: initial platform supportKarl Palsson5-0/+392
Have some demo code using lptim, lpuart, exti and rtc mostly working. It glitches into undefined exceptions, so it's a little concerning, but... it's all cross checked against RM0440_rev7, so it's pretty good. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16stm32l4: fix exti register mapKarl Palsson1-0/+1
Missing a gap before the second section continued. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16stm32_uart: add write_blocking helperKarl Palsson1-0/+6
A nice easy basic helper for "I just wannna wite a char now!"
2022-04-16platforms: stm32wb: add LPUART1Karl Palsson1-0/+3
2022-04-16FIXME: platforms: stm32l4: fix all rcc enables, add lptimKarl Palsson3-2/+78
FIXME: LPTIM should be split out, rcc should squish to earlier, as early as we can with other rcc fixes,post the last dev_v2 merge.
2022-04-16platforms: stm32l4: Fix interrupts, enableKarl Palsson2-41/+73
Need to actually include the l4 file to start building! When I copied all the peripheral addresses out of the ref man, I ignored the RCC interrupts and platform define. Fix that now, against RM0351_rev9 Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16platform: stm32l4: more variantsKarl Palsson1-0/+20
Will need more work though, as there's L476xC with 256K flash, 128K ram, and L432xC with 256K flash, 64K ram. But that's tomorrow's problem, I'm using a 476xG... Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16WIP: stm32_hsem: lock get/release helpersKarl Palsson1-0/+8
2022-04-16WIP: stm32_pwr: LPMS helpersKarl Palsson1-0/+7
2022-04-16timer: add LPTIM definitionsKarl Palsson2-0/+18
Add them to the stm32wb platform as well. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16rcc: add "disable" methods for low powerKarl Palsson2-0/+10
Some people might like to turn peripherals back off again. We have all the machinery in place, so make it easy for them. Signed-off-by: Karl Palsson <karlp@etactica.com>
2022-04-16stm32f7: Add more peripherals.Vegard Storheil Eriksen5-4/+93
2022-04-16async: Add preliminary time scheduler.Vegard Storheil Eriksen3-0/+140
2022-04-16gdb_plugins/mmio: Add mmio_ref helper.Vegard Storheil Eriksen1-0/+13
2022-04-16display: stm32: Add LTDC support.Vegard Storheil Eriksen5-0/+83
2022-04-16i2c: stm32: Add v2 support.Vegard Storheil Eriksen7-191/+72
2022-01-26stm32_ipcc: helper methods to ease porting ST codeKarl Palsson1-0/+32
Make it a litle easier to read for some bits that are constantly checked. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32wb: rtc: initial registersKarl Palsson5-0/+75
Backup registers are just hardcoded to 32, which is the max seen. Note that the STM32WB only has 20! I've captured that in the platform yaml, even though it's not used anywhere (yet?) Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32l1: initial support, incompleteKarl Palsson4-0/+242
2022-01-26stm32_syscfg: convert to modern.Karl Palsson8-39/+54
Includes the f4, l0 and wb. f4 renames MEMRM to MEMRMP to be both consistent with other parts and consistent with ref man. Retested on the WB, but l0 and f4 code was simply moved. For yaml files, given how varied syscfg is, we default to using the family name as the type, but still allow overriding via explicit type in the yaml file if desired. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26syscfg: stm32wb: legacy implementationKarl Palsson1-0/+23
Functional, after much hair tearing. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32_gpio: provide port and pin numbersKarl Palsson1-4/+12
Accessing Pin.n and Pin.get_portnum() will give you values suitable for use with EXTI and similar places. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32l4: add basic platform fileKarl Palsson3-0/+268
While checking STM32WB, this was easy enough to just transcribe while working. Untested on real hardware. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26build: provide a "LAKS" defineKarl Palsson1-1/+2
maybe you're doing something wrong, or maybe you're doing something so so right. Hand people a salmon and let them make that decision. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32wb: cal: add Flash UID64Karl Palsson1-0/+8
At least the constants to get started. Note that RM0434r8 says that 0x27 is for revision "B" but rev9 says it's not revision "X" (Presumably B nomenclature has been dropped?)
2022-01-26stm32wb: exti: initial registersKarl Palsson5-0/+61
Basic registers to start with, a lot of commonality, but extra registers on the WB. Signed-off-by <karlp@tweak.net.au>
2022-01-26stm32wb: wpan/ipcc/hsem: initial registersKarl Palsson6-0/+88
Not sure if "wpan" is the right directory for them, but they didn't feel like they warranted their own directory each. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32wb: pwr: initial registersKarl Palsson5-0/+70
No helpers, just the register map. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26platforms/stm32/wb: sort existing peripheralsKarl Palsson3-15/+15
Makes merging and diffing easier later.
2022-01-26rcc: stm32wb: add remaining regs and max speed helperKarl Palsson3-11/+105
Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2 doesn't exceed 32MHz though. Adds the remaining RCC registers and bits as well. Most of these are not useful, as you can't really/meaningfully deliver software to CPU2, but some of them are used/required by the ST provided WPAN middleware. Signed-off-by: Karl Palsson <karlp@etactica.com> Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26cal: basic temp/vrefint constsKarl Palsson1-0/+24
No API, just pointers to the calibration data and their associated constants.
2022-01-26debug: add overload for writing floats to stimulus portsKarl Palsson1-0/+9
Overload all the things! Signed-off-by: Karl Palsson <karlp@etactica.com>
2022-01-26cortex-debug: support itm blocking for char tooKarl Palsson1-0/+8
less end user casting, more back end c++ magic
2022-01-26cortex-debug: add blocking ITM helpers.Karl Palsson1-0/+26
Sometimes you really would like to slow things down to get trace out.
2022-01-26stm32f3: add ADC1/2 and ADC3/4 convencience aliasesKarl Palsson1-0/+4
So you don't always have to refer to ADC12 or ADC34
2022-01-26stm32wb: use ADC_COMMON1 for consistent namingKarl Palsson1-1/+1
2022-01-26stm32_rcc: allow aliases for enables.Karl Palsson5-222/+222
By flipping the name/number definition, we can define aliases such as ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have code that both matches reference manuals, and also code that matches between lines. runtime tested on WB, compile tested on F3. Signed-off-by: Karl Palsson <karlp@etactica.com>
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