laks - Microcontroller support library.

Age	Commit message (Collapse)	Author	Files	Lines
2022-01-26	stm32wb: exti: initial registers	Karl Palsson	1	-0/+5
	Basic registers to start with, a lot of commonality, but extra registers on the WB. Signed-off-by <karlp@tweak.net.au>
2022-01-26	stm32wb: wpan/ipcc/hsem: initial registers	Karl Palsson	1	-0/+8
	Not sure if "wpan" is the right directory for them, but they didn't feel like they warranted their own directory each. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26	stm32wb: pwr: initial registers	Karl Palsson	1	-0/+5
	No helpers, just the register map. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26	platforms/stm32/wb: sort existing peripherals	Karl Palsson	1	-13/+13
	Makes merging and diffing easier later.
2022-01-26	rcc: stm32wb: add remaining regs and max speed helper	Karl Palsson	1	-1/+54
	Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2 doesn't exceed 32MHz though. Adds the remaining RCC registers and bits as well. Most of these are not useful, as you can't really/meaningfully deliver software to CPU2, but some of them are used/required by the ST provided WPAN middleware. Signed-off-by: Karl Palsson <karlp@etactica.com> Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26	stm32_rcc: allow aliases for enables.	Karl Palsson	1	-38/+38
	By flipping the name/number definition, we can define aliases such as ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have code that both matches reference manuals, and also code that matches between lines. runtime tested on WB, compile tested on F3. Signed-off-by: Karl Palsson <karlp@etactica.com>
2022-01-26	flash: convert to new style	Karl Palsson	1	-0/+5

2021-09-17	gpio: stm32: default to v2	Karl Palsson	1	-5/+0
	v2 is for everyone except f1, so avoid the yaml spam. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16	gpio: Generate instances from platform spec.	Vegard Storheil Eriksen	1	-0/+5

2021-09-16	gpio: stm32wb: add base addresses to platform	Karl Palsson	1	-0/+12
	This is not hooked up to anything yet, but would be where the GPIOs get connected if they are converted to new style. There's no reason to pull this commit by itself though!
2021-09-16	timer: stm32: default to v1	Karl Palsson	1	-4/+0
	"All" parts so far have the v1 timer api, so default to that, but allow overriding, instead of requiring it to be specified every time. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16	timer: convert to new style and add WB	Karl Palsson	1	-0/+14
	Stub f1 and f3 platform files have been added to preserve the collected timer base addresses, even though those platforms aren't actually supported in laks yet. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16	dma: convert to new style, add DMAMUX	Karl Palsson	1	-0/+13
	DMAMUX is a channel/source muxer available on L4+,L5,H7,G0,G4,WB and WL parts. Signed-of-by: Karl Palsson <karlp@etactica.com>
2021-09-16	rcc: Fix enable register access for devices with multiple registers for the ↵	Vegard Storheil Eriksen	1	-1/+1
	same bus.
2021-09-16	platforms: add stm32wb	Karl Palsson	1	-0/+161
	Basic RCC and memory map support. Signed-off-by: Karl Palsson <karlp@etactica.com>