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path: root/platforms/stm32/wb.yaml
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2022-04-16platforms: stm32wb: add LPUART1Karl Palsson1-0/+3
2022-04-16timer: add LPTIM definitionsKarl Palsson1-0/+6
Add them to the stm32wb platform as well. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32wb: rtc: initial registersKarl Palsson1-0/+5
Backup registers are just hardcoded to 32, which is the max seen. Note that the STM32WB only has 20! I've captured that in the platform yaml, even though it's not used anywhere (yet?) Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32_syscfg: convert to modern.Karl Palsson1-0/+4
Includes the f4, l0 and wb. f4 renames MEMRM to MEMRMP to be both consistent with other parts and consistent with ref man. Retested on the WB, but l0 and f4 code was simply moved. For yaml files, given how varied syscfg is, we default to using the family name as the type, but still allow overriding via explicit type in the yaml file if desired. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32wb: exti: initial registersKarl Palsson1-0/+5
Basic registers to start with, a lot of commonality, but extra registers on the WB. Signed-off-by <karlp@tweak.net.au>
2022-01-26stm32wb: wpan/ipcc/hsem: initial registersKarl Palsson1-0/+8
Not sure if "wpan" is the right directory for them, but they didn't feel like they warranted their own directory each. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32wb: pwr: initial registersKarl Palsson1-0/+5
No helpers, just the register map. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26platforms/stm32/wb: sort existing peripheralsKarl Palsson1-13/+13
Makes merging and diffing easier later.
2022-01-26rcc: stm32wb: add remaining regs and max speed helperKarl Palsson1-1/+54
Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2 doesn't exceed 32MHz though. Adds the remaining RCC registers and bits as well. Most of these are not useful, as you can't really/meaningfully deliver software to CPU2, but some of them are used/required by the ST provided WPAN middleware. Signed-off-by: Karl Palsson <karlp@etactica.com> Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32_rcc: allow aliases for enables.Karl Palsson1-38/+38
By flipping the name/number definition, we can define aliases such as ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have code that both matches reference manuals, and also code that matches between lines. runtime tested on WB, compile tested on F3. Signed-off-by: Karl Palsson <karlp@etactica.com>
2022-01-26flash: convert to new styleKarl Palsson1-0/+5
2021-09-17gpio: stm32: default to v2Karl Palsson1-5/+0
v2 is for everyone except f1, so avoid the yaml spam. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16gpio: Generate instances from platform spec.Vegard Storheil Eriksen1-0/+5
2021-09-16gpio: stm32wb: add base addresses to platformKarl Palsson1-0/+12
This is not hooked up to anything yet, but would be where the GPIOs get connected if they are converted to new style. There's no reason to pull this commit by itself though!
2021-09-16timer: stm32: default to v1Karl Palsson1-4/+0
"All" parts so far have the v1 timer api, so default to that, but allow overriding, instead of requiring it to be specified every time. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16timer: convert to new style and add WBKarl Palsson1-0/+14
Stub f1 and f3 platform files have been added to preserve the collected timer base addresses, even though those platforms aren't actually supported in laks yet. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16dma: convert to new style, add DMAMUXKarl Palsson1-0/+13
DMAMUX is a channel/source muxer available on L4+,L5,H7,G0,G4,WB and WL parts. Signed-of-by: Karl Palsson <karlp@etactica.com>
2021-09-16rcc: Fix enable register access for devices with multiple registers for the ↵Vegard Storheil Eriksen1-1/+1
same bus.
2021-09-16platforms: add stm32wbKarl Palsson1-0/+161
Basic RCC and memory map support. Signed-off-by: Karl Palsson <karlp@etactica.com>
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