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2022-01-26stm32wb: pwr: initial registersKarl Palsson1-0/+5
No helpers, just the register map. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26platforms/stm32/wb: sort existing peripheralsKarl Palsson1-13/+13
Makes merging and diffing easier later.
2022-01-26rcc: stm32wb: add remaining regs and max speed helperKarl Palsson1-1/+54
Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2 doesn't exceed 32MHz though. Adds the remaining RCC registers and bits as well. Most of these are not useful, as you can't really/meaningfully deliver software to CPU2, but some of them are used/required by the ST provided WPAN middleware. Signed-off-by: Karl Palsson <karlp@etactica.com> Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32f3: add ADC1/2 and ADC3/4 convencience aliasesKarl Palsson1-0/+4
So you don't always have to refer to ADC12 or ADC34
2022-01-26stm32_rcc: allow aliases for enables.Karl Palsson4-221/+221
By flipping the name/number definition, we can define aliases such as ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have code that both matches reference manuals, and also code that matches between lines. runtime tested on WB, compile tested on F3. Signed-off-by: Karl Palsson <karlp@etactica.com>
2022-01-26flash: convert to new styleKarl Palsson6-0/+30
2022-01-20platforms: stm32f3: make functionalKarl Palsson2-2/+232
Sufficient for blinking leds. Not much else tested yet. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-17gpio: stm32: default to v2Karl Palsson5-31/+0
v2 is for everyone except f1, so avoid the yaml spam. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16gpio: Generate instances from platform spec.Vegard Storheil Eriksen6-0/+107
2021-09-16gpio: stm32wb: add base addresses to platformKarl Palsson1-0/+12
This is not hooked up to anything yet, but would be where the GPIOs get connected if they are converted to new style. There's no reason to pull this commit by itself though!
2021-09-16timer: stm32: default to v1Karl Palsson4-28/+0
"All" parts so far have the v1 timer api, so default to that, but allow overriding, instead of requiring it to be specified every time. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16timer: convert to new style and add WBKarl Palsson4-0/+95
Stub f1 and f3 platform files have been added to preserve the collected timer base addresses, even though those platforms aren't actually supported in laks yet. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16dma: convert to new style, add DMAMUXKarl Palsson2-0/+21
DMAMUX is a channel/source muxer available on L4+,L5,H7,G0,G4,WB and WL parts. Signed-of-by: Karl Palsson <karlp@etactica.com>
2021-09-16rcc: Fix enable register access for devices with multiple registers for the ↵Vegard Storheil Eriksen1-1/+1
same bus.
2021-09-16platforms: add stm32wbKarl Palsson2-0/+165
Basic RCC and memory map support. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-15platforms: Improve STM32F42x support.Vegard Storheil Eriksen1-0/+7
2021-09-15platforms: Add initial STM32F7 support.Vegard Storheil Eriksen2-1/+228
2021-09-15uart: Generate instances from platform spec.Vegard Storheil Eriksen1-1/+3
2021-01-26rcc: Generate enables from platform spec.Vegard Storheil Eriksen1-0/+73
2021-01-22interrupt: Refactor to be more flexible.Vegard Storheil Eriksen1-92/+93
2021-01-16interrupt: Generate interrupts from platform spec.Vegard Storheil Eriksen1-0/+93
2021-01-16usb: Generate instances from platform spec.Vegard Storheil Eriksen1-0/+13
2021-01-07build: Generate linker script.Vegard Storheil Eriksen1-2/+0
2021-01-07build: Add platform spec framework.Vegard Storheil Eriksen2-0/+38
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 12:23:37 +0100