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2022-09-10stm32g4: Add OPAMP.Vegard Storheil Eriksen1-0/+4
2022-09-10stm32g4: Rename DMAMUX1 to DMAMUX.Vegard Storheil Eriksen1-2/+2
2022-07-28stm32_adc: Rename common blocks to ADC12 and ADC345 respectively.Vegard Storheil Eriksen3-5/+11
2022-07-27stm32g4: Add 512k variant.Vegard Storheil Eriksen1-0/+7
2022-07-27stm32g4: Add ADC.Vegard Storheil Eriksen1-0/+23
2022-07-27adc: convert to new styleKarl Palsson4-0/+50
Converted the old STM32 headers to new style and copied offsets to platform data. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16stm32g4: initial platform supportKarl Palsson2-0/+324
Have some demo code using lptim, lpuart, exti and rtc mostly working. It glitches into undefined exceptions, so it's a little concerning, but... it's all cross checked against RM0440_rev7, so it's pretty good. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16platforms: stm32wb: add LPUART1Karl Palsson1-0/+3
2022-04-16FIXME: platforms: stm32l4: fix all rcc enables, add lptimKarl Palsson1-2/+21
FIXME: LPTIM should be split out, rcc should squish to earlier, as early as we can with other rcc fixes,post the last dev_v2 merge.
2022-04-16platforms: stm32l4: Fix interrupts, enableKarl Palsson2-41/+73
Need to actually include the l4 file to start building! When I copied all the peripheral addresses out of the ref man, I ignored the RCC interrupts and platform define. Fix that now, against RM0351_rev9 Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16platform: stm32l4: more variantsKarl Palsson1-0/+20
Will need more work though, as there's L476xC with 256K flash, 128K ram, and L432xC with 256K flash, 64K ram. But that's tomorrow's problem, I'm using a 476xG... Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16timer: add LPTIM definitionsKarl Palsson1-0/+6
Add them to the stm32wb platform as well. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16stm32f7: Add more peripherals.Vegard Storheil Eriksen1-2/+84
2022-04-16display: stm32: Add LTDC support.Vegard Storheil Eriksen1-0/+4
2022-04-16i2c: stm32: Add v2 support.Vegard Storheil Eriksen1-0/+14
2022-01-26stm32wb: rtc: initial registersKarl Palsson1-0/+5
Backup registers are just hardcoded to 32, which is the max seen. Note that the STM32WB only has 20! I've captured that in the platform yaml, even though it's not used anywhere (yet?) Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32l1: initial support, incompleteKarl Palsson2-0/+217
2022-01-26stm32_syscfg: convert to modern.Karl Palsson3-0/+12
Includes the f4, l0 and wb. f4 renames MEMRM to MEMRMP to be both consistent with other parts and consistent with ref man. Retested on the WB, but l0 and f4 code was simply moved. For yaml files, given how varied syscfg is, we default to using the family name as the type, but still allow overriding via explicit type in the yaml file if desired. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32l4: add basic platform fileKarl Palsson1-0/+238
While checking STM32WB, this was easy enough to just transcribe while working. Untested on real hardware. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32wb: exti: initial registersKarl Palsson1-0/+5
Basic registers to start with, a lot of commonality, but extra registers on the WB. Signed-off-by <karlp@tweak.net.au>
2022-01-26stm32wb: wpan/ipcc/hsem: initial registersKarl Palsson1-0/+8
Not sure if "wpan" is the right directory for them, but they didn't feel like they warranted their own directory each. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32wb: pwr: initial registersKarl Palsson1-0/+5
No helpers, just the register map. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26platforms/stm32/wb: sort existing peripheralsKarl Palsson1-13/+13
Makes merging and diffing easier later.
2022-01-26rcc: stm32wb: add remaining regs and max speed helperKarl Palsson1-1/+54
Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2 doesn't exceed 32MHz though. Adds the remaining RCC registers and bits as well. Most of these are not useful, as you can't really/meaningfully deliver software to CPU2, but some of them are used/required by the ST provided WPAN middleware. Signed-off-by: Karl Palsson <karlp@etactica.com> Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32f3: add ADC1/2 and ADC3/4 convencience aliasesKarl Palsson1-0/+4
So you don't always have to refer to ADC12 or ADC34
2022-01-26stm32_rcc: allow aliases for enables.Karl Palsson4-221/+221
By flipping the name/number definition, we can define aliases such as ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have code that both matches reference manuals, and also code that matches between lines. runtime tested on WB, compile tested on F3. Signed-off-by: Karl Palsson <karlp@etactica.com>
2022-01-26flash: convert to new styleKarl Palsson6-0/+30
2022-01-20platforms: stm32f3: make functionalKarl Palsson2-2/+232
Sufficient for blinking leds. Not much else tested yet. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-17gpio: stm32: default to v2Karl Palsson5-31/+0
v2 is for everyone except f1, so avoid the yaml spam. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16gpio: Generate instances from platform spec.Vegard Storheil Eriksen6-0/+107
2021-09-16gpio: stm32wb: add base addresses to platformKarl Palsson1-0/+12
This is not hooked up to anything yet, but would be where the GPIOs get connected if they are converted to new style. There's no reason to pull this commit by itself though!
2021-09-16timer: stm32: default to v1Karl Palsson4-28/+0
"All" parts so far have the v1 timer api, so default to that, but allow overriding, instead of requiring it to be specified every time. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16timer: convert to new style and add WBKarl Palsson4-0/+95
Stub f1 and f3 platform files have been added to preserve the collected timer base addresses, even though those platforms aren't actually supported in laks yet. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16dma: convert to new style, add DMAMUXKarl Palsson2-0/+21
DMAMUX is a channel/source muxer available on L4+,L5,H7,G0,G4,WB and WL parts. Signed-of-by: Karl Palsson <karlp@etactica.com>
2021-09-16rcc: Fix enable register access for devices with multiple registers for the ↵Vegard Storheil Eriksen1-1/+1
same bus.
2021-09-16platforms: add stm32wbKarl Palsson2-0/+165
Basic RCC and memory map support. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-15platforms: Improve STM32F42x support.Vegard Storheil Eriksen1-0/+7
2021-09-15platforms: Add initial STM32F7 support.Vegard Storheil Eriksen2-1/+228
2021-09-15uart: Generate instances from platform spec.Vegard Storheil Eriksen1-1/+3
2021-01-26rcc: Generate enables from platform spec.Vegard Storheil Eriksen1-0/+73
2021-01-22interrupt: Refactor to be more flexible.Vegard Storheil Eriksen1-92/+93
2021-01-16interrupt: Generate interrupts from platform spec.Vegard Storheil Eriksen1-0/+93
2021-01-16usb: Generate instances from platform spec.Vegard Storheil Eriksen1-0/+13
2021-01-07build: Generate linker script.Vegard Storheil Eriksen1-2/+0
2021-01-07build: Add platform spec framework.Vegard Storheil Eriksen2-0/+38
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