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Have some demo code using lptim, lpuart, exti and rtc mostly working.
It glitches into undefined exceptions, so it's a little concerning,
but... it's all cross checked against RM0440_rev7, so it's pretty good.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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FIXME: LPTIM should be split out, rcc should squish to earlier, as early
as we can with other rcc fixes,post the last dev_v2 merge.
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Need to actually include the l4 file to start building!
When I copied all the peripheral addresses out of the ref man, I ignored
the RCC interrupts and platform define. Fix that now, against
RM0351_rev9
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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Will need more work though, as there's L476xC with 256K flash, 128K ram,
and L432xC with 256K flash, 64K ram. But that's tomorrow's problem, I'm
using a 476xG...
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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Add them to the stm32wb platform as well.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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Backup registers are just hardcoded to 32, which is the max seen.
Note that the STM32WB only has 20! I've captured that in the platform
yaml, even though it's not used anywhere (yet?)
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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Includes the f4, l0 and wb. f4 renames MEMRM to MEMRMP to be both
consistent with other parts and consistent with ref man.
Retested on the WB, but l0 and f4 code was simply moved.
For yaml files, given how varied syscfg is, we default to using the
family name as the type, but still allow overriding via explicit type in
the yaml file if desired.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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While checking STM32WB, this was easy enough to just transcribe while
working. Untested on real hardware.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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Basic registers to start with, a lot of commonality, but extra registers
on the WB.
Signed-off-by <karlp@tweak.net.au>
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Not sure if "wpan" is the right directory for them, but they didn't feel
like they warranted their own directory each.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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No helpers, just the register map.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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Makes merging and diffing easier later.
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Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2
doesn't exceed 32MHz though.
Adds the remaining RCC registers and bits as well. Most of these are not
useful, as you can't really/meaningfully deliver software to CPU2, but
some of them are used/required by the ST provided WPAN middleware.
Signed-off-by: Karl Palsson <karlp@etactica.com>
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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So you don't always have to refer to ADC12 or ADC34
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By flipping the name/number definition, we can define aliases such as
ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have
code that both matches reference manuals, and also code that matches
between lines.
runtime tested on WB, compile tested on F3.
Signed-off-by: Karl Palsson <karlp@etactica.com>
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Sufficient for blinking leds. Not much else tested yet.
Signed-off-by: Karl Palsson <karlp@etactica.com>
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v2 is for everyone except f1, so avoid the yaml spam.
Signed-off-by: Karl Palsson <karlp@etactica.com>
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This is not hooked up to anything yet, but would be where the GPIOs get
connected if they are converted to new style. There's no reason to pull
this commit by itself though!
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"All" parts so far have the v1 timer api, so default to that, but allow
overriding, instead of requiring it to be specified every time.
Signed-off-by: Karl Palsson <karlp@etactica.com>
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Stub f1 and f3 platform files have been added to preserve the collected
timer base addresses, even though those platforms aren't actually
supported in laks yet.
Signed-off-by: Karl Palsson <karlp@etactica.com>
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DMAMUX is a channel/source muxer available on L4+,L5,H7,G0,G4,WB and WL
parts.
Signed-of-by: Karl Palsson <karlp@etactica.com>
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same bus.
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Basic RCC and memory map support.
Signed-off-by: Karl Palsson <karlp@etactica.com>
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