Age | Commit message (Collapse) | Author | Files | Lines |
|
|
|
Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2
doesn't exceed 32MHz though.
Adds the remaining RCC registers and bits as well. Most of these are not
useful, as you can't really/meaningfully deliver software to CPU2, but
some of them are used/required by the ST provided WPAN middleware.
Signed-off-by: Karl Palsson <karlp@etactica.com>
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
|
|
Working with dma and timers. This preserves the somewhat dubious
decision that ADC clock for F1 and F3 should be 12Mhz. It can always be
overridden later.
|
|
Sufficient for blinking leds. Not much else tested yet.
Signed-off-by: Karl Palsson <karlp@etactica.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Most sources are split off from suzumebachi project revision 2fc77d2 as is with some path changes. New build rules introduced.
|