| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-04-16 | rcc: add "disable" methods for low power | Karl Palsson | 2 | -0/+10 | |
| Some people might like to turn peripherals back off again. We have all the machinery in place, so make it easy for them. Signed-off-by: Karl Palsson <karlp@etactica.com> | |||||
| 2022-04-16 | stm32f7: Add more peripherals. | Vegard Storheil Eriksen | 3 | -2/+5 | |
| 2022-01-26 | stm32l1: initial support, incomplete | Karl Palsson | 1 | -0/+18 | |
| 2022-01-26 | stm32_syscfg: convert to modern. | Karl Palsson | 1 | -19/+0 | |
| Includes the f4, l0 and wb. f4 renames MEMRM to MEMRMP to be both consistent with other parts and consistent with ref man. Retested on the WB, but l0 and f4 code was simply moved. For yaml files, given how varied syscfg is, we default to using the family name as the type, but still allow overriding via explicit type in the yaml file if desired. Signed-off-by: Karl Palsson <karlp@tweak.net.au> | |||||
| 2022-01-26 | stm32l4: add basic platform file | Karl Palsson | 1 | -0/+15 | |
| While checking STM32WB, this was easy enough to just transcribe while working. Untested on real hardware. Signed-off-by: Karl Palsson <karlp@tweak.net.au> | |||||
| 2022-01-26 | rcc: stm32wb: add remaining regs and max speed helper | Karl Palsson | 2 | -10/+51 | |
| Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2 doesn't exceed 32MHz though. Adds the remaining RCC registers and bits as well. Most of these are not useful, as you can't really/meaningfully deliver software to CPU2, but some of them are used/required by the ST provided WPAN middleware. Signed-off-by: Karl Palsson <karlp@etactica.com> Signed-off-by: Karl Palsson <karlp@tweak.net.au> | |||||
| 2022-01-26 | stm32_rcc: allow aliases for enables. | Karl Palsson | 1 | -1/+1 | |
| By flipping the name/number definition, we can define aliases such as ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have code that both matches reference manuals, and also code that matches between lines. runtime tested on WB, compile tested on F3. Signed-off-by: Karl Palsson <karlp@etactica.com> | |||||
| 2022-01-26 | flash: convert to new style | Karl Palsson | 4 | -26/+46 | |
| 2022-01-20 | adc: stm32f3: expand and verify | Karl Palsson | 1 | -3/+7 | |
| Working with dma and timers. This preserves the somewhat dubious decision that ADC clock for F1 and F3 should be 12Mhz. It can always be overridden later. | |||||
| 2022-01-20 | platforms: stm32f3: make functional | Karl Palsson | 1 | -5/+5 | |
| Sufficient for blinking leds. Not much else tested yet. Signed-off-by: Karl Palsson <karlp@etactica.com> | |||||
| 2021-09-16 | flash: stm32wb: oldstyle: add register map and basic init | Karl Palsson | 2 | -0/+31 | |
| Flash hasn't yet been ported to new style. Signed-off-by: Karl Palsson <karlp@tweak.net.au> | |||||
| 2021-09-16 | rcc: Fix enable register access for devices with multiple registers for the ↵ | Vegard Storheil Eriksen | 1 | -1/+1 | |
| same bus. | |||||
| 2021-09-16 | platforms: add stm32wb | Karl Palsson | 1 | -0/+46 | |
| Basic RCC and memory map support. Signed-off-by: Karl Palsson <karlp@etactica.com> | |||||
| 2021-09-16 | rcc: include a static file with function prototypes | Karl Palsson | 2 | -0/+7 | |
| Authors modifying rcc.cpp should add their protos here as desired. Signed-off-by: Karl Palsson <karlp@tweak.net.au> | |||||
| 2021-09-16 | generators: clearly mark generated files | Karl Palsson | 1 | -0/+2 | |
| This makes it easier for end users to see where files have come from. Signed-off-by: Karl Palsson <karlp@tweak.net.au> | |||||
| 2021-09-15 | platforms: Improve STM32F42x support. | Vegard Storheil Eriksen | 1 | -2/+2 | |
| 2021-01-26 | rcc: Generate enables from platform spec. | Vegard Storheil Eriksen | 5 | -472/+213 | |
| 2019-03-19 | Added STM32F042 support. | Vegard Storheil Eriksen | 4 | -4/+14 | |
| 2019-03-19 | Added STM32F0 support. | Vegard Storheil Eriksen | 1 | -4/+72 | |
| 2017-05-14 | STM32F4: Added rcc_init() overload with sysclk argument. | Vegard Storheil Eriksen | 2 | -0/+44 | |
| 2016-08-19 | STM32L0: Fixed typo in FLASH_PEKEYR. | Vegard Storheil Eriksen | 1 | -1/+1 | |
| 2016-08-18 | STM32L0: Add CRS definition. | Vegard Storheil Eriksen | 1 | -0/+30 | |
| 2016-08-18 | Add STM32L0 to rcc_init(). | Vegard Storheil Eriksen | 2 | -0/+35 | |
| 2016-08-18 | Added STM32L0 support. | Vegard Storheil Eriksen | 2 | -3/+91 | |
| 2012-12-29 | Fixed F1 RCC bug. | Vegard Storheil Eriksen | 1 | -1/+1 | |
| 2012-12-10 | Added ethernet and syscfg register definitions. | Vegard Storheil Eriksen | 2 | -0/+22 | |
| 2012-11-19 | Added support for F3. | Vegard Storheil Eriksen | 4 | -6/+69 | |
| 2012-10-09 | Add OTGHSULPI clock gate definition. | Vegard Storheil Eriksen | 1 | -14/+15 | |
| 2012-09-05 | Renamed RCC.IOPx to RCC.GPIOx for F1. | Vegard Storheil Eriksen | 1 | -7/+7 | |
| 2012-08-07 | Initial import. | Vegard Storheil Eriksen | 4 | -0/+315 | |
| Most sources are split off from suzumebachi project revision 2fc77d2 as is with some path changes. New build rules introduced. | |||||
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index : laks | |
| Microcontroller support library. | Vegard Storheil Eriksen |
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