From 1155f57710a068efbdc7fdd167ac4e44dd54ec7f Mon Sep 17 00:00:00 2001
From: Karl Palsson <karlp@tweak.net.au>
Date: Wed, 12 Jan 2022 17:30:15 +0000
Subject: stm32wb: rtc: initial registers

Backup registers are just hardcoded to 32, which is the max seen.
Note that the STM32WB only has 20!  I've captured that in the platform
yaml, even though it's not used anywhere (yet?)

Signed-off-by: Karl Palsson <karlp@tweak.net.au>
---
 .gitignore              |  1 +
 SConscript              |  1 +
 platforms/stm32/wb.yaml |  5 +++++
 rtc/SConscript          | 24 ++++++++++++++++++++++++
 rtc/stm32_rtc.h         | 44 ++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 75 insertions(+)
 create mode 100644 rtc/SConscript
 create mode 100644 rtc/stm32_rtc.h

diff --git a/.gitignore b/.gitignore
index f70630d..46bc223 100644
--- a/.gitignore
+++ b/.gitignore
@@ -17,6 +17,7 @@ pwr/pwr.h
 rcc/flash.h
 rcc/rcc.h
 rcc/rcc_enums.h
+rtc/rtc.h
 syscfg/syscfg.h
 timer/timer.h
 usb/usb.h
diff --git a/SConscript b/SConscript
index 27a885c..01679d9 100644
--- a/SConscript
+++ b/SConscript
@@ -13,6 +13,7 @@ env.Append(
 		env.SConscript('interrupt/SConscript'),
 		env.SConscript('pwr/SConscript'),
 		env.SConscript('rcc/SConscript'),
+		env.SConscript('rtc/SConscript'),
 		env.SConscript('syscfg/SConscript'),
 		env.SConscript('timer/SConscript'),
 		env.SConscript('uart/SConscript'),
diff --git a/platforms/stm32/wb.yaml b/platforms/stm32/wb.yaml
index d3590a5..81005f4 100644
--- a/platforms/stm32/wb.yaml
+++ b/platforms/stm32/wb.yaml
@@ -76,6 +76,11 @@
         type: wb
         offset: 0x58000400
 
+    stm32_rtc:
+      RTC:
+        offset: 0x40002800
+        backup_count: 20
+
     stm32_syscfg:
       SYSCFG:
         offset: 0x40010000
diff --git a/rtc/SConscript b/rtc/SConscript
new file mode 100644
index 0000000..f7956c0
--- /dev/null
+++ b/rtc/SConscript
@@ -0,0 +1,24 @@
+Import('env')
+
+headers = []
+instances = []
+sources = []
+aliases = {}
+
+periph = env['PLATFORM_SPEC'].get('periph', {})
+
+if 'stm32_rtc' in periph:
+    headers.append('stm32_rtc.h')
+    for name, data in periph['stm32_rtc'].items():
+        # Default to version 2, with subseconds, the most common form.
+        real_type = data.get('type', 'v2ss')
+        instances.append({
+            'type': 'STM32_RTC_t<STM32_RTC_reg_%s_t>' % real_type,
+            'name': name,
+            'args': [data['offset']],
+        })
+
+env.Jinja2('rtc.h', '../templates/periph_instances.h.j2', headers = headers, instances = instances, aliases = aliases)
+
+Return('sources')
+
diff --git a/rtc/stm32_rtc.h b/rtc/stm32_rtc.h
new file mode 100644
index 0000000..bc78128
--- /dev/null
+++ b/rtc/stm32_rtc.h
@@ -0,0 +1,44 @@
+#pragma once
+
+#include <mmio/mmio.h>
+
+struct STM32_RTC_reg_v2ss_t {
+	volatile uint32_t TR;
+	volatile uint32_t DR;
+	volatile uint32_t CR;
+	volatile uint32_t ISR;
+	volatile uint32_t PRER;
+	volatile uint32_t WUTR;
+	uint32_t _reserved1;
+	volatile uint32_t ALRMAR;
+	volatile uint32_t ALRMBR;
+	volatile uint32_t WPR;
+	volatile uint32_t SSR;
+	volatile uint32_t SHIFTR;
+	volatile uint32_t TSTR;
+	volatile uint32_t TSDR;
+	volatile uint32_t TSSSR;
+	volatile uint32_t CALR;
+	volatile uint32_t TAMPCR;
+	volatile uint32_t ALRMASSR;
+	volatile uint32_t ALRMBSSR;
+	volatile uint32_t OR;
+	volatile uint32_t BKP[32]; /* max known 32, might be less, check DS */
+};
+
+template <typename T>
+class STM32_RTC_t : public mmio_ptr<T> {
+	public:
+		using mmio_ptr<T>::ptr;
+
+		void lock(void) const {
+			ptr()->WPR = 0x99;  // Doesn't matter...
+		}
+
+		void unlock(void) const {
+			ptr()->WPR = 0xCA;
+			ptr()->WPR = 0x53;
+		}
+
+};
+
-- 
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