From 24507af1a99f66ded76e8796de5bae35c7c0b567 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 20 Sep 2021 11:23:29 +0000 Subject: stm32_rcc: allow aliases for enables. By flipping the name/number definition, we can define aliases such as ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have code that both matches reference manuals, and also code that matches between lines. runtime tested on WB, compile tested on F3. Signed-off-by: Karl Palsson --- platforms/stm32/f3.yaml | 94 ++++++++++++++--------------- platforms/stm32/f4.yaml | 116 +++++++++++++++++------------------ platforms/stm32/f7.yaml | 156 ++++++++++++++++++++++++------------------------ platforms/stm32/wb.yaml | 76 +++++++++++------------ rcc/rcc_enums.h.j2 | 2 +- 5 files changed, 222 insertions(+), 222 deletions(-) diff --git a/platforms/stm32/f3.yaml b/platforms/stm32/f3.yaml index 52b00bd..ad14a9a 100644 --- a/platforms/stm32/f3.yaml +++ b/platforms/stm32/f3.yaml @@ -118,57 +118,57 @@ type: f3 bus: AHB: - 0: DMA1 - 1: DMA2 - 2: SRAM - 4: FLITF - 5: FSMC - 6: CRC - 16: GPIOH - 17: GPIOA - 18: GPIOB - 19: GPIOC - 20: GPIOD - 21: GPIOE - 22: GPIOF - 23: GPIOG - 24: TSC - 28: ADC12 - 29: ADC34 + DMA1: 0 + DMA2: 1 + SRAM: 2 + FLITF: 4 + FSMC: 5 + CRC: 6 + GPIOH: 16 + GPIOA: 17 + GPIOB: 18 + GPIOC: 19 + GPIOD: 20 + GPIOE: 21 + GPIOF: 22 + GPIOG: 23 + TSC: 24 + ADC12: 28 + ADC34: 29 APB1: - 0: TIM2 - 1: TIM3 - 2: TIM4 - 4: TIM6 - 5: TIM7 - 11: WWDG - 14: SPI2 - 15: SPI3 - 17: USART2 - 18: USART3 - 19: UART4 - 20: UART5 - 21: I2C1 - 22: I2C2 - 23: USB - 25: CAN - 26: DAC2 - 28: PWR - 29: DAC1 - 30: I2C3 + TIM2: 0 + TIM3: 1 + TIM4: 2 + TIM6: 4 + TIM7: 5 + WWDG: 11 + SPI2: 14 + SPI3: 15 + USART2: 17 + USART3: 18 + UART4: 19 + UART5: 20 + I2C1: 21 + I2C2: 22 + USB: 23 + CAN: 25 + DAC2: 26 + PWR: 28 + DAC1: 29 + I2C3: 30 APB2: - 0: SYSCFG - 11: TIM1 - 12: SPI1 - 13: TIM8 - 14: USART1 - 15: SPI4 - 16: TIM15 - 17: TIM16 - 18: TIM17 - 20: TIM10 + SYSCFG: 0 + TIM1: 11 + SPI1: 12 + TIM8: 13 + USART1: 14 + SPI4: 15 + TIM15: 16 + TIM16: 17 + TIM17: 18 + TIM10: 20 interrupt: irq: diff --git a/platforms/stm32/f4.yaml b/platforms/stm32/f4.yaml index 2aca27c..f9ff092 100644 --- a/platforms/stm32/f4.yaml +++ b/platforms/stm32/f4.yaml @@ -100,72 +100,72 @@ type: f4 bus: AHB1: - 0: GPIOA - 1: GPIOB - 2: GPIOC - 3: GPIOD - 4: GPIOE - 5: GPIOF - 6: GPIOG - 7: GPIOH - 8: GPIOI - 12: CRC - 21: DMA1 - 22: DMA2 - 25: ETHMAC - 26: ETHMACTX - 27: ETHMACRX - 28: ETHMACPTP - 29: OTGHS - 30: OTGHSULPI + GPIOA: 0 + GPIOB: 1 + GPIOC: 2 + GPIOD: 3 + GPIOE: 4 + GPIOF: 5 + GPIOG: 6 + GPIOH: 7 + GPIOI: 8 + CRC: 12 + DMA1: 21 + DMA2: 22 + ETHMAC: 25 + ETHMACTX: 26 + ETHMACRX: 27 + ETHMACPTP: 28 + OTGHS: 29 + OTGHSULPI: 30 AHB2: - 0: DCMI - 4: CRYP - 5: HASH - 6: RNG - 7: OTGFS + DCMI: 0 + CRYP: 4 + HASH: 5 + RNG: 6 + OTGFS: 7 AHB3: - 0: FSMC + FSMC: 0 APB1: - 0: TIM2 - 1: TIM3 - 2: TIM4 - 3: TIM5 - 4: TIM6 - 5: TIM7 - 6: TIM12 - 7: TIM13 - 8: TIM14 - 11: WWDG - 14: SPI2 - 15: SPI3 - 17: USART2 - 18: USART3 - 19: UART4 - 20: UART5 - 21: I2C1 - 22: I2C2 - 23: I2C3 - 25: CAN1 - 26: CAN2 - 28: PWR - 29: DAC + TIM2: 0 + TIM3: 1 + TIM4: 2 + TIM5: 3 + TIM6: 4 + TIM7: 5 + TIM12: 6 + TIM13: 7 + TIM14: 8 + WWDG: 11 + SPI2: 14 + SPI3: 15 + USART2: 17 + USART3: 18 + UART4: 19 + UART5: 20 + I2C1: 21 + I2C2: 22 + I2C3: 23 + CAN1: 25 + CAN2: 26 + PWR: 28 + DAC: 29 APB2: - 0: TIM1 - 1: TIM8 - 4: USART1 - 5: USART6 - 8: ADC - 11: SDIO - 12: SPI1 - 14: SYSCFG - 16: TIM9 - 17: TIM10 - 18: TIM11 + TIM1: 0 + TIM8: 1 + USART1: 4 + USART6: 5 + ADC: 8 + SDIO: 11 + SPI1: 12 + SYSCFG: 14 + TIM9: 16 + TIM10: 17 + TIM11: 18 interrupt: irq: diff --git a/platforms/stm32/f7.yaml b/platforms/stm32/f7.yaml index 7c8e04d..abf821a 100644 --- a/platforms/stm32/f7.yaml +++ b/platforms/stm32/f7.yaml @@ -32,92 +32,92 @@ type: f4 bus: AHB1: - 0: GPIOA - 1: GPIOB - 2: GPIOC - 3: GPIOD - 4: GPIOE - 5: GPIOF - 6: GPIOG - 7: GPIOH - 8: GPIOI - 8: GPIOJ - 8: GPIOK - 12: CRC - 18: BKPSRAM - 20: DTCMRAM - 21: DMA1 - 22: DMA2 - 23: DMA2D - 25: ETHMAC - 26: ETHMACTX - 27: ETHMACRX - 28: ETHMACPTP - 29: OTGHS - 30: OTGHSULPI + GPIOA: 0 + GPIOB: 1 + GPIOC: 2 + GPIOD: 3 + GPIOE: 4 + GPIOF: 5 + GPIOG: 6 + GPIOH: 7 + GPIOI: 8 + GPIOJ: 8 + GPIOK: 8 + CRC: 12 + BKPSRAM: 18 + DTCMRAM: 20 + DMA1: 21 + DMA2: 22 + DMA2D: 23 + ETHMAC: 25 + ETHMACTX: 26 + ETHMACRX: 27 + ETHMACPTP: 28 + OTGHS: 29 + OTGHSULPI: 30 AHB2: - 0: DCMI - 4: CRYP - 5: HASH - 6: RNG - 7: OTGFS + DCMI: 0 + CRYP: 4 + HASH: 5 + RNG: 6 + OTGFS: 7 AHB3: - 0: FMC - 1: QSPI + FMC: 0 + QSPI: 1 APB1: - 0: TIM2 - 1: TIM3 - 2: TIM4 - 3: TIM5 - 4: TIM6 - 5: TIM7 - 6: TIM12 - 7: TIM13 - 8: TIM14 - 9: LPTIM1 - 11: WWDG - 14: SPI2 - 15: SPI3 - 16: SPDIFRX - 17: USART2 - 18: USART3 - 19: UART4 - 20: UART5 - 21: I2C1 - 22: I2C2 - 23: I2C3 - 24: I2C4 - 25: CAN1 - 26: CAN2 - 27: CEC - 28: PWR - 29: DAC - 30: UART7 - 31: UART8 + TIM2: 0 + TIM3: 1 + TIM4: 2 + TIM5: 3 + TIM6: 4 + TIM7: 5 + TIM12: 6 + TIM13: 7 + TIM14: 8 + LPTIM1: 9 + WWDG: 11 + SPI2: 14 + SPI3: 15 + SPDIFRX: 16 + USART2: 17 + USART3: 18 + UART4: 19 + UART5: 20 + I2C1: 21 + I2C2: 22 + I2C3: 23 + I2C4: 24 + CAN1: 25 + CAN2: 26 + CEC: 27 + PWR: 28 + DAC: 29 + UART7: 30 + UART8: 31 APB2: - 0: TIM1 - 1: TIM8 - 4: USART1 - 5: USART6 - 8: ADC1 - 9: ADC2 - 10: ADC3 - 11: SDMMC1 - 12: SPI1 - 13: SPI4 - 14: SYSCFG - 16: TIM9 - 17: TIM10 - 18: TIM11 - 20: SPI5 - 21: SPI6 - 22: SAI1 - 23: SAI2 - 26: LTDC + TIM1: 0 + TIM8: 1 + USART1: 4 + USART6: 5 + ADC1: 8 + ADC2: 9 + ADC3: 10 + SDMMC1: 11 + SPI1: 12 + SPI4: 13 + SYSCFG: 14 + TIM9: 16 + TIM10: 17 + TIM11: 18 + SPI5: 20 + SPI6: 21 + SAI1: 22 + SAI2: 23 + LTDC: 26 interrupt: irq: diff --git a/platforms/stm32/wb.yaml b/platforms/stm32/wb.yaml index d8fb1f3..f27db8a 100644 --- a/platforms/stm32/wb.yaml +++ b/platforms/stm32/wb.yaml @@ -79,54 +79,54 @@ type: wb bus: AHB1: - 0: DMA1 - 1: DMA2 - 2: DMAMUX1 - 12: CRC - 16: TSC + DMA1: 0 + DMA2: 1 + DMAMUX1: 2 + CRC: 12 + TSC: 16 AHB2: - 0: GPIOA - 1: GPIOB - 2: GPIOC - 3: GPIOD - 4: GPIOE - 7: GPIOH - 13: ADC1 + GPIOA: 0 + GPIOB: 1 + GPIOC: 2 + GPIOD: 3 + GPIOE: 4 + GPIOH: 7 + ADC1: 13 AHB3: - 8: QUADSPI - 16: PKA - 17: AES2 - 18: RNG - 19: HSEM - 20: IPCC - 25: FLASH - 7: OTGFS + QUADSPI: 8 + PKA: 16 + AES2: 17 + RNG: 18 + HSEM: 19 + IPCC: 20 + FLASH: 25 + OTGFS: 7 APB1_1: - 0: TIM2 - 9: LCD - 10: RTCAPB - 11: WWDG - 14: SPI2 - 21: I2C1 - 23: I2C3 - 24: CRS - 26: USB - 31: LPTIM1 + TIM2: 0 + LCD: 9 + RTCAPB: 10 + WWDG: 11 + SPI2: 14 + I2C1: 21 + I2C3: 23 + CRS: 24 + USB: 26 + LPTIM1: 31 APB1_2: - 0: LPUART1 - 5: LPTIM2 + LPUART1: 0 + LPTIM2: 5 APB2: - 11: TIM1 - 12: SPI1 - 14: USART1 - 17: TIM16 - 18: TIM17 - 21: SAI1 + TIM1: 11 + SPI1: 12 + USART1: 14 + TIM16: 17 + TIM17: 18 + SAI1: 21 interrupt: irq: diff --git a/rcc/rcc_enums.h.j2 b/rcc/rcc_enums.h.j2 index 97e85b9..a4965b0 100644 --- a/rcc/rcc_enums.h.j2 +++ b/rcc/rcc_enums.h.j2 @@ -5,7 +5,7 @@ namespace rcc { {% for bus, devices in buses.items() %} enum {{ bus }}_dev { - {% for num, name in devices.items() %} + {% for name, num in devices.items() %} {{ name }} = 1 << {{ num }}, {% endfor %} }; -- cgit v1.2.3