From cad5bd6501868f9532d5b4a227ca156f9c9d1d8e Mon Sep 17 00:00:00 2001
From: Vegard Storheil Eriksen <zyp@jvnv.net>
Date: Thu, 16 Sep 2021 11:09:30 +0200
Subject: Added NRF52 support.

---
 gpio/gpio_nrf.h | 83 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644 gpio/gpio_nrf.h

(limited to 'gpio/gpio_nrf.h')

diff --git a/gpio/gpio_nrf.h b/gpio/gpio_nrf.h
new file mode 100644
index 0000000..44c85f4
--- /dev/null
+++ b/gpio/gpio_nrf.h
@@ -0,0 +1,83 @@
+#ifndef LAKS_GPIO_GPIO_NRF_H
+#define LAKS_GPIO_GPIO_NRF_H
+
+#include <stdint.h>
+
+struct GPIO_reg_t {
+	uint32_t _reserved;
+	volatile uint32_t OUT;
+	volatile uint32_t OUTSET;
+	volatile uint32_t OUTCLR;
+	volatile uint32_t IN;
+	volatile uint32_t DIR;
+	volatile uint32_t DIRSET;
+	volatile uint32_t DIRCLR;
+	volatile uint32_t LATCH;
+	volatile uint32_t DETECTMODE;
+	uint32_t _reserved_1[118];
+	volatile uint32_t PIN_CNF[32];
+};
+
+class GPIO_t {
+	public:
+		GPIO_reg_t& reg;
+		
+		class Pin {
+			private:
+				const GPIO_t& g;
+				int n;
+			
+			public:
+				constexpr Pin(const GPIO_t& gpio, int pin) : g(gpio), n(pin) {}
+				
+				enum Mode {
+					Input,
+					Output,
+				};
+				
+				void set_mode(Mode m) {
+					switch(m) {
+						case Input:
+							g.reg.DIRCLR = 1 << n;
+							break;
+						case Output:
+							g.reg.DIRSET = 1 << n;
+							break;
+					}
+				}
+				
+				void on() {
+					g.reg.OUTSET = 1 << n;
+				}
+				
+				void off() {
+					g.reg.OUTCLR = 1 << n;
+				}
+				
+				void set(bool value) {
+					if(value) {
+						on();
+					} else {
+						off();
+					}
+				}
+				
+				bool get() {
+					return g.reg.IN & (1 << n);
+				}
+				
+				void toggle() {
+					set(!(g.reg.OUT & (1 << n)));
+				}
+		};
+		
+		constexpr GPIO_t(uint32_t reg_addr) : reg(*(GPIO_reg_t*)(reg_addr + 0x500)) {}
+		
+		constexpr Pin operator[](int pin) {
+			return Pin(*this, pin);
+		}
+};
+
+typedef GPIO_t::Pin Pin;
+
+#endif
-- 
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