From 968937d0d937487ab301f017c145889fc0e94692 Mon Sep 17 00:00:00 2001
From: Vegard Storheil Eriksen <zyp@jvnv.net>
Date: Wed, 15 Sep 2021 23:16:11 +0200
Subject: platforms: Add initial RISC-V/GD32V support.

---
 interrupt/vectors_clic.cpp.j2 | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 interrupt/vectors_clic.cpp.j2

(limited to 'interrupt/vectors_clic.cpp.j2')

diff --git a/interrupt/vectors_clic.cpp.j2 b/interrupt/vectors_clic.cpp.j2
new file mode 100644
index 0000000..7f9dd9f
--- /dev/null
+++ b/interrupt/vectors_clic.cpp.j2
@@ -0,0 +1,23 @@
+#include "interrupt.h"
+
+interrupt::vector_t vectors_clic[] = {
+    {% for i in range(interrupts.irq | max + 1 if interrupts.irq else interrupts.internal | max + 1 if interrupts.internal else 0) %}
+        {% if i in interrupts.internal %}
+            interrupt::handler<interrupt::internal::{{ interrupts.internal[i] }}>,
+        {% elif i in interrupts.irq %}
+            interrupt::handler<interrupt::irq::{{ interrupts.irq[i] }}>,
+        {% else %}
+            0,
+        {% endif %}
+    {% endfor %}
+};
+
+interrupt::vector_t vectors_exception[] = {
+    {% for i in range(interrupts.exception | max + 1 if interrupts.exception else 0) %}
+        {% if i in interrupts.exception %}
+            interrupt::handler<interrupt::exception::{{ interrupts.exception[i] }}>,
+        {% else %}
+            0,
+        {% endif %}
+    {% endfor %}
+};
-- 
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