From 1a38973eb8fd0f889f7c272e9ef183687034d550 Mon Sep 17 00:00:00 2001
From: Vegard Storheil Eriksen <zyp@jvnv.net>
Date: Fri, 22 Jan 2021 01:13:44 +0100
Subject: interrupt: Refactor to be more flexible.

---
 platforms/stm32/f4.yaml | 185 ++++++++++++++++++++++++------------------------
 1 file changed, 93 insertions(+), 92 deletions(-)

(limited to 'platforms/stm32')

diff --git a/platforms/stm32/f4.yaml b/platforms/stm32/f4.yaml
index c132524..8a632f1 100644
--- a/platforms/stm32/f4.yaml
+++ b/platforms/stm32/f4.yaml
@@ -34,98 +34,99 @@
       OTG_HS:
         offset: 0x40040000
 
-  irq:
-    0: WWDG
-    1: PVD
-    2: TAMP_STAMP
-    3: RTC_WKUP
-    4: FLASH
-    5: RCC
-    6: EXTI0
-    7: EXTI1
-    8: EXTI2
-    9: EXTI3
-    10: EXTI4
-    11: DMA1_Stream0
-    12: DMA1_Stream1
-    13: DMA1_Stream2
-    14: DMA1_Stream3
-    15: DMA1_Stream4
-    16: DMA1_Stream5
-    17: DMA1_Stream6
-    18: ADC
-    19: CAN1_TX
-    20: CAN1_RX0
-    21: CAN1_RX1
-    22: CAN1_SCE
-    23: EXTI9_5
-    24: TIM1_BRK_TIM9
-    25: TIM1_UP_TIM10
-    26: TIM1_TRG_COM_TIM11
-    27: TIM1_CC
-    28: TIM2
-    29: TIM3
-    30: TIM4
-    31: I2C1_EV
-    32: I2C1_ER
-    33: I2C2_EV
-    34: I2C2_ER
-    35: SPI1
-    36: SPI2
-    37: USART1
-    38: USART2
-    39: USART3
-    40: EXTI15_10
-    41: RTC_Alarm
-    42: OTG_FS_WKUP
-    43: TIM8_BRK_TIM12
-    44: TIM8_UP_TIM13
-    45: TIM8_TRG_COM_TIM14
-    46: TIM8_CC
-    47: DMA1_Stream7
-    48: FSMC
-    49: SDIO
-    50: TIM5
-    51: SPI3
-    52: UART4
-    53: UART5
-    54: TIM6_DAC
-    55: TIM7
-    56: DMA2_Stream0
-    57: DMA2_Stream1
-    58: DMA2_Stream2
-    59: DMA2_Stream3
-    60: DMA2_Stream4
-    61: ETH
-    62: ETH_WKUP
-    63: CAN2_TX
-    64: CAN2_RX0
-    65: CAN2_RX1
-    66: CAN2_SCE
-    67: OTG_FS
-    68: DMA2_Stream5
-    69: DMA2_Stream6
-    70: DMA2_Stream7
-    71: USART6
-    72: I2C3_EV
-    73: I2C3_ER
-    74: OTG_HS_EP1_OUT
-    75: OTG_HS_EP1_IN
-    76: OTG_HS_WKUP
-    77: OTG_HS
-    78: DCMI
-    79: CRYP
-    80: HASH_RNG
-    81: FPU
-    82: UART7
-    83: UART8
-    84: SPI4
-    85: SPI5
-    86: SPI6
-    87: SAI1
-    88: LCD_TFT
-    89: LCD_TFT_ERR
-    90: DMA2D
+  interrupt:
+    irq:
+      0: WWDG
+      1: PVD
+      2: TAMP_STAMP
+      3: RTC_WKUP
+      4: FLASH
+      5: RCC
+      6: EXTI0
+      7: EXTI1
+      8: EXTI2
+      9: EXTI3
+      10: EXTI4
+      11: DMA1_Stream0
+      12: DMA1_Stream1
+      13: DMA1_Stream2
+      14: DMA1_Stream3
+      15: DMA1_Stream4
+      16: DMA1_Stream5
+      17: DMA1_Stream6
+      18: ADC
+      19: CAN1_TX
+      20: CAN1_RX0
+      21: CAN1_RX1
+      22: CAN1_SCE
+      23: EXTI9_5
+      24: TIM1_BRK_TIM9
+      25: TIM1_UP_TIM10
+      26: TIM1_TRG_COM_TIM11
+      27: TIM1_CC
+      28: TIM2
+      29: TIM3
+      30: TIM4
+      31: I2C1_EV
+      32: I2C1_ER
+      33: I2C2_EV
+      34: I2C2_ER
+      35: SPI1
+      36: SPI2
+      37: USART1
+      38: USART2
+      39: USART3
+      40: EXTI15_10
+      41: RTC_Alarm
+      42: OTG_FS_WKUP
+      43: TIM8_BRK_TIM12
+      44: TIM8_UP_TIM13
+      45: TIM8_TRG_COM_TIM14
+      46: TIM8_CC
+      47: DMA1_Stream7
+      48: FSMC
+      49: SDIO
+      50: TIM5
+      51: SPI3
+      52: UART4
+      53: UART5
+      54: TIM6_DAC
+      55: TIM7
+      56: DMA2_Stream0
+      57: DMA2_Stream1
+      58: DMA2_Stream2
+      59: DMA2_Stream3
+      60: DMA2_Stream4
+      61: ETH
+      62: ETH_WKUP
+      63: CAN2_TX
+      64: CAN2_RX0
+      65: CAN2_RX1
+      66: CAN2_SCE
+      67: OTG_FS
+      68: DMA2_Stream5
+      69: DMA2_Stream6
+      70: DMA2_Stream7
+      71: USART6
+      72: I2C3_EV
+      73: I2C3_ER
+      74: OTG_HS_EP1_OUT
+      75: OTG_HS_EP1_IN
+      76: OTG_HS_WKUP
+      77: OTG_HS
+      78: DCMI
+      79: CRYP
+      80: HASH_RNG
+      81: FPU
+      82: UART7
+      83: UART8
+      84: SPI4
+      85: SPI5
+      86: SPI6
+      87: SAI1
+      88: LCD_TFT
+      89: LCD_TFT_ERR
+      90: DMA2D
 
   define:
     - STM32F4
-- 
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