From d60be6f83a4519afc0875f28f0959c51edb4fbeb Mon Sep 17 00:00:00 2001
From: Vegard Storheil Eriksen <zyp@jvnv.net>
Date: Sat, 10 Sep 2022 20:19:37 +0200
Subject: riscv: Add rv32ima and rv32im.

---
 platforms/riscv.yaml | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

(limited to 'platforms')

diff --git a/platforms/riscv.yaml b/platforms/riscv.yaml
index f66a3ef..5764af2 100644
--- a/platforms/riscv.yaml
+++ b/platforms/riscv.yaml
@@ -4,8 +4,24 @@
   cflags:
     - -march=rv32imac
     - -mabi=ilp32
-    - -msmall-data-limit=0
+
+- match:
+    cpu: rv32ima
   
+  cflags:
+    - -march=rv32ima
+    - -mabi=ilp32
+
+- match:
+    cpu: rv32im
+
+  cflags:
+    - -march=rv32im
+    - -mabi=ilp32
+
+- cflags:
+    - -msmall-data-limit=0
+
   interrupt:
     exception:
       0: InstructionMisaligned
-- 
cgit v1.2.3