From 3d4618b786594af253a2cf972452e79ae230eccc Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 17 Sep 2021 11:14:21 +0000 Subject: rcc: stm32wb: add remaining regs and max speed helper Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2 doesn't exceed 32MHz though. Adds the remaining RCC registers and bits as well. Most of these are not useful, as you can't really/meaningfully deliver software to CPU2, but some of them are used/required by the ST provided WPAN middleware. Signed-off-by: Karl Palsson Signed-off-by: Karl Palsson --- rcc/rcc.cpp | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'rcc/rcc.cpp') diff --git a/rcc/rcc.cpp b/rcc/rcc.cpp index 794b1ee..67bb948 100644 --- a/rcc/rcc.cpp +++ b/rcc/rcc.cpp @@ -90,7 +90,31 @@ void rcc_init() { // Select HSI48 for USB. RCC->CCIPR |= 1 << 26; - + + #elif defined(STM32WB) + // Enable HSE. + RCC->CR |= (1<<16); + while(!(RCC->CR & (1<<17))); + + // Configure and enable PLL. + // R=2, Q = 2, P = 2, M = 2, N = 8, src=HSE + const auto m = 2; + const auto n = 8; + const auto p = 2; + const auto q = 2; + const auto r = 2; + + RCC->PLLCFGR = ((r-1)<<29) | (1<<28) | ((q-1)<<25) | ((p-1)<<17) | (n<<8) | ((m-1)<<4) | (3<<0); + RCC->CR |= (1<<24); + while(!(RCC->CR & (1<<25))); + + // 64MHz/2 to keep CPU2 in bounds + RCC->EXTCFGR |= (0b1000 << 4); + + // Switch to PLL. + RCC->CFGR |= 0x3; + while((RCC->CFGR & (3 << 2)) != (3 << 2)); // SWS = PLL + #endif } -- cgit v1.2.3