From c993afa6df80e96bd1fcf96f3ea45f9721a13334 Mon Sep 17 00:00:00 2001 From: Vegard Storheil Eriksen Date: Mon, 25 Jan 2021 14:23:11 +0100 Subject: rcc: Generate enables from platform spec. --- rcc/rcc.cpp | 88 ++++++++++++++++++++++++++++++------------------------------- 1 file changed, 44 insertions(+), 44 deletions(-) (limited to 'rcc/rcc.cpp') diff --git a/rcc/rcc.cpp b/rcc/rcc.cpp index 65faf33..5a7e29e 100644 --- a/rcc/rcc.cpp +++ b/rcc/rcc.cpp @@ -9,83 +9,83 @@ void rcc_init() { #if defined(STM32F1) || defined(STM32F3) // Enable HSE. - RCC.CR |= 0x10000; - while(!(RCC.CR & 0x20000)); + RCC->CR |= 0x10000; + while(!(RCC->CR & 0x20000)); // Configure and enable PLL. - RCC.CFGR = 0x1d0000; - RCC.CR |= 0x1000000; - while(!(RCC.CR & 0x2000000)); + RCC->CFGR = 0x1d0000; + RCC->CR |= 0x1000000; + while(!(RCC->CR & 0x2000000)); // Switch to PLL. - RCC.CFGR |= 0x2; - while(!(RCC.CFGR & 0x8)); + RCC->CFGR |= 0x2; + while(!(RCC->CFGR & 0x8)); // Set APB1 prescaler to /2. - RCC.CFGR |= 0x400; + RCC->CFGR |= 0x400; // Set ADCCLK prescaler to /6. - RCC.CFGR |= 0x8000; + RCC->CFGR |= 0x8000; #elif defined(STM32F4) // Enable HSE. - RCC.CR |= 0x10000; - while(!(RCC.CR & 0x20000)); + RCC->CR |= 0x10000; + while(!(RCC->CR & 0x20000)); // Configure and enable PLL. - RCC.PLLCFGR = 0x20400000 | (7 << 24) | (2 * 168 << 6) | 8; - RCC.CR |= 0x1000000; - while(!(RCC.CR & 0x2000000)); + RCC->PLLCFGR = 0x20400000 | (7 << 24) | (2 * 168 << 6) | 8; + RCC->CR |= 0x1000000; + while(!(RCC->CR & 0x2000000)); // Switch to PLL. - RCC.CFGR |= 0x2; - while(!(RCC.CFGR & 0x8)); + RCC->CFGR |= 0x2; + while(!(RCC->CFGR & 0x8)); // Set APB1 prescaler to /4. - RCC.CFGR |= 5 << 10; + RCC->CFGR |= 5 << 10; // Set APB2 prescaler to /2. - RCC.CFGR |= 4 << 13; + RCC->CFGR |= 4 << 13; #elif defined(STM32F0) // Enable HSI48. - RCC.CR2 |= 1 << 16; // HSI48ON - while(!(RCC.CR2 & (1 << 17))); // HSI48RDY + RCC->CR2 |= 1 << 16; // HSI48ON + while(!(RCC->CR2 & (1 << 17))); // HSI48RDY // Switch to HSI48. - RCC.CFGR |= 3 << 0; // SW = HSI48 - while((RCC.CFGR & (3 << 2)) != (3 << 2)); // SWS = HSI48 + RCC->CFGR |= 3 << 0; // SW = HSI48 + while((RCC->CFGR & (3 << 2)) != (3 << 2)); // SWS = HSI48 #elif defined(STM32L0) // Enable HSI16. - RCC.CR |= 1 << 0; // HSI16ON - while(!(RCC.CR & (1 << 2))); // HSI16RDYF + RCC->CR |= 1 << 0; // HSI16ON + while(!(RCC->CR & (1 << 2))); // HSI16RDYF // Configure PLL. - RCC.CFGR |= (1 << 22) | (1 << 18) | (0 << 16); // PLLDIV = /2, PLLMUL = 4x, PLLSRC = HSI16 + RCC->CFGR |= (1 << 22) | (1 << 18) | (0 << 16); // PLLDIV = /2, PLLMUL = 4x, PLLSRC = HSI16 // Enable PLL. - RCC.CR |= 1 << 24; // PLLON - while(!(RCC.CR & (1 << 25))); // PLLRDY + RCC->CR |= 1 << 24; // PLLON + while(!(RCC->CR & (1 << 25))); // PLLRDY // Switch to PLL. - RCC.CFGR |= 3 << 0; // SW = PLL - while((RCC.CFGR & (3 << 2)) != (3 << 2)); // SWS = PLL + RCC->CFGR |= 3 << 0; // SW = PLL + while((RCC->CFGR & (3 << 2)) != (3 << 2)); // SWS = PLL // Enable VREFINT for HSI48. - RCC.enable(RCC.SYSCFG); + RCC->enable(RCC->SYSCFG); SYSCFG.CFGR3 |= (1 << 13) | (1 << 0); // ENREF_HSI48, EN_VREFINT while(!(SYSCFG.CFGR3 & (1 << 26))); // REF_HSI48_RDYF // Enable HSI48. - RCC.CRRCR |= 1 << 0; // HSI48ON - while(!(RCC.CRRCR & (1 << 1))); // HSI48RDY + RCC->CRRCR |= 1 << 0; // HSI48ON + while(!(RCC->CRRCR & (1 << 1))); // HSI48RDY // Select HSI48 for USB. - RCC.CCIPR |= 1 << 26; + RCC->CCIPR |= 1 << 26; #endif } @@ -99,30 +99,30 @@ void rcc_init(uint32_t osc_mhz, uint32_t sysclk_mhz) { uint32_t pllp = sysclk_mhz > 192 / 2 ? 0 : 1; // Enable HSE. - RCC.CR |= 0x10000; - while(!(RCC.CR & 0x20000)); + RCC->CR |= 0x10000; + while(!(RCC->CR & 0x20000)); // Configure and enable PLL. - RCC.PLLCFGR = 0x20400000 | ((pll_mhz / 48) << 24) | (pllp << 16) | (pll_mhz << 6) | osc_mhz; - RCC.CR |= 0x1000000; - while(!(RCC.CR & 0x2000000)); + RCC->PLLCFGR = 0x20400000 | ((pll_mhz / 48) << 24) | (pllp << 16) | (pll_mhz << 6) | osc_mhz; + RCC->CR |= 0x1000000; + while(!(RCC->CR & 0x2000000)); // Switch to PLL. - RCC.CFGR |= 0x2; - while(!(RCC.CFGR & 0x8)); + RCC->CFGR |= 0x2; + while(!(RCC->CFGR & 0x8)); if(sysclk_mhz > 84) { // Set APB1 prescaler to /4. - RCC.CFGR |= 5 << 10; // PPRE1 + RCC->CFGR |= 5 << 10; // PPRE1 // Set APB2 prescaler to /2. - RCC.CFGR |= 4 << 13; // PPRE2 + RCC->CFGR |= 4 << 13; // PPRE2 } else { // Set APB1 prescaler to /2. - RCC.CFGR |= 4 << 10; // PPRE1 + RCC->CFGR |= 4 << 10; // PPRE1 // Set APB2 prescaler to /1. - RCC.CFGR |= 0 << 13; // PPRE2 + RCC->CFGR |= 0 << 13; // PPRE2 } } -- cgit v1.2.3