From e586c178073b9a0fee90d5fc8e795d266ebd7b7d Mon Sep 17 00:00:00 2001 From: Vegard Storheil Eriksen Date: Tue, 7 Aug 2012 16:50:46 +0200 Subject: Initial import. Most sources are split off from suzumebachi project revision 2fc77d2 as is with some path changes. New build rules introduced. --- rcc/rcc.cpp | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 rcc/rcc.cpp (limited to 'rcc/rcc.cpp') diff --git a/rcc/rcc.cpp b/rcc/rcc.cpp new file mode 100644 index 0000000..57b8f7d --- /dev/null +++ b/rcc/rcc.cpp @@ -0,0 +1,51 @@ +#include "rcc.h" +#include "flash.h" + +void rcc_init() { + // Initialize flash. + flash_init(); + + #if defined(STM32F1) + + // Enable HSE. + RCC.CR |= 0x10000; + while(RCC.CR & 0x20000); + + // Configure and enable PLL. + RCC.CFGR = 0x1d0000; + RCC.CR |= 0x1000000; + while(!(RCC.CR & 0x2000000)); + + // Switch to PLL. + RCC.CFGR |= 0x2; + while(!(RCC.CFGR & 0x8)); + + // Set APB1 prescaler to /2. + RCC.CFGR |= 0x400; + + // Set ADCCLK prescaler to /6. + RCC.CFGR |= 0x8000; + + #elif defined(STM32F4) + + // Enable HSE. + RCC.CR |= 0x10000; + while(!(RCC.CR & 0x20000)); + + // Configure and enable PLL. + RCC.PLLCFGR = 0x20400000 | (7 << 24) | (2 * 168 << 6) | 8; + RCC.CR |= 0x1000000; + while(!(RCC.CR & 0x2000000)); + + // Switch to PLL. + RCC.CFGR |= 0x2; + while(!(RCC.CFGR & 0x8)); + + // Set APB1 prescaler to /4. + RCC.CFGR |= 5 << 10; + + // Set APB2 prescaler to /2. + RCC.CFGR |= 4 << 13; + + #endif +} -- cgit v1.2.3