From b34efc66f164816d37d47f52efd591555eefdd5c Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 6 Jan 2022 23:30:28 +0000 Subject: stm32wb: wpan/ipcc/hsem: initial registers Not sure if "wpan" is the right directory for them, but they didn't feel like they warranted their own directory each. Signed-off-by: Karl Palsson --- wpan/SConscript | 29 +++++++++++++++++++++++++++++ wpan/stm32_hsem.h | 26 ++++++++++++++++++++++++++ wpan/stm32_ipcc.h | 22 ++++++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 wpan/SConscript create mode 100644 wpan/stm32_hsem.h create mode 100644 wpan/stm32_ipcc.h (limited to 'wpan') diff --git a/wpan/SConscript b/wpan/SConscript new file mode 100644 index 0000000..d9e854a --- /dev/null +++ b/wpan/SConscript @@ -0,0 +1,29 @@ +Import('env') + +periph = env['PLATFORM_SPEC'].get('periph', {}) + +headers, instances, sources, aliases = [], [], [], {} +if 'stm32_hsem' in periph: + headers.append('stm32_hsem.h') + for name, data in periph['stm32_hsem'].items(): + real_type = data.get('type', 'v1') # Default + instances.append({ + 'type': 'STM32_HSEM_t' % real_type, + 'name': name, + 'args': [data['offset']], + }) +env.Jinja2('hsem.h', '../templates/periph_instances.h.j2', headers = headers, instances = instances, aliases = aliases) + +headers, instances, sources, aliases = [], [], [], {} +if 'stm32_ipcc' in periph: + headers.append('stm32_ipcc.h') + for name, data in periph['stm32_ipcc'].items(): + real_type = data.get('type', 'v1') # Default + instances.append({ + 'type': 'STM32_IPCC_t' % real_type, + 'name': name, + 'args': [data['offset']], + }) +env.Jinja2('ipcc.h', '../templates/periph_instances.h.j2', headers = headers, instances = instances, aliases = aliases) + +Return('sources') \ No newline at end of file diff --git a/wpan/stm32_hsem.h b/wpan/stm32_hsem.h new file mode 100644 index 0000000..f8d9dd3 --- /dev/null +++ b/wpan/stm32_hsem.h @@ -0,0 +1,26 @@ +#pragma once + +#include +#include + +struct STM32_HSEM_reg_v1_t { + volatile uint32_t R[32]; + volatile uint32_t RLR[32]; + volatile uint32_t C1IER; + volatile uint32_t C1ICR; + volatile uint32_t C1ISR; + volatile uint32_t C1MISR; + volatile uint32_t C2IER; + volatile uint32_t C2ICR; + volatile uint32_t C2ISR; + volatile uint32_t C2MISR; + uint32_t _reserved[8]; + volatile uint32_t CR; + volatile uint32_t KEYR; +}; + +template +class STM32_HSEM_t : public mmio_ptr { + public: + using mmio_ptr::ptr; +}; \ No newline at end of file diff --git a/wpan/stm32_ipcc.h b/wpan/stm32_ipcc.h new file mode 100644 index 0000000..e264d8b --- /dev/null +++ b/wpan/stm32_ipcc.h @@ -0,0 +1,22 @@ +#pragma once + +#include +#include + + +struct STM32_IPCC_reg_v1_t { + volatile uint32_t C1CR; + volatile uint32_t C1MR; + volatile uint32_t C1SCR; + volatile uint32_t C1TOC2SR; + volatile uint32_t C2CR; + volatile uint32_t C2MR; + volatile uint32_t C2SCR; + volatile uint32_t C2TOC1SR; +}; + +template +class STM32_IPCC_t : public mmio_ptr { + public: + using mmio_ptr::ptr; +}; -- cgit v1.2.3