From 89225b336c715d3b11bcc0d5b4ef0b80c2bd28f9 Mon Sep 17 00:00:00 2001 From: Vegard Storheil Eriksen Date: Sat, 3 Dec 2011 19:06:29 +0100 Subject: hal/stm32.h --- hal/stm32.h | 164 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/hal/stm32.h b/hal/stm32.h index 8144e80..3f39bed 100644 --- a/hal/stm32.h +++ b/hal/stm32.h @@ -34,6 +34,7 @@ struct SCB_t { static SCB_t& SCB = *(SCB_t*)0xe000ed00; struct RCC_t { + #if defined(STM32F1) volatile uint32_t CR; volatile uint32_t CFGR; volatile uint32_t CIR; @@ -44,7 +45,44 @@ struct RCC_t { volatile uint32_t APB1ENR; volatile uint32_t BDCR; volatile uint32_t CSR; + #elif defined(STM32F4) + volatile uint32_t CR; + volatile uint32_t PLLCFGR; + volatile uint32_t CFGR; + volatile uint32_t CIR; + volatile uint32_t AHB1RSTR; + volatile uint32_t AHB2RSTR; + volatile uint32_t AHB3RSTR; + volatile uint32_t AHB4RSTR; // Reserved + volatile uint32_t APB1RSTR; + volatile uint32_t APB2RSTR; + volatile uint32_t APB3RSTR; // Reserved + volatile uint32_t APB4RSTR; // Reserved + volatile uint32_t AHB1ENR; + volatile uint32_t AHB2ENR; + volatile uint32_t AHB3ENR; + volatile uint32_t AHB4ENR; // Reserved + volatile uint32_t APB1ENR; + volatile uint32_t APB2ENR; + volatile uint32_t APB3ENR; // Reserved + volatile uint32_t APB4ENR; // Reserved + volatile uint32_t AHB1LPENR; + volatile uint32_t AHB2LPENR; + volatile uint32_t AHB3LPENR; + volatile uint32_t AHB4LPENR; // Reserved + volatile uint32_t APB1LPENR; + volatile uint32_t APB2LPENR; + volatile uint32_t APB3LPENR; // Reserved + volatile uint32_t APB4LPENR; // Reserved + volatile uint32_t BDCR; + volatile uint32_t CSR; + volatile uint32_t _1; + volatile uint32_t _2; + volatile uint32_t SSCGR; + volatile uint32_t PLLI2SCFGR; + #endif + #if defined(STM32F1) enum AHB_dev { DMA1 = 1 << 0, DMA2 = 1 << 1, @@ -101,11 +139,94 @@ struct RCC_t { TIM10 = 1 << 20, TIM11 = 1 << 21 }; + #elif defined(STM32F4) + enum AHB1_dev { + GPIOA = 1 << 0, + GPIOB = 1 << 1, + GPIOC = 1 << 2, + GPIOD = 1 << 3, + GPIOE = 1 << 4, + GPIOF = 1 << 5, + GPIOG = 1 << 6, + GPIOH = 1 << 7, + GPIOI = 1 << 8, + CRC = 1 << 12, + DMA1 = 1 << 21, + DMA2 = 1 << 22, + ETHMAC = 1 << 25, + OTGHS = 1 << 29, + }; + + enum AHB2_dev { + DCMI = 1 << 0, + CRYP = 1 << 4, + HASH = 1 << 5, + RNG = 1 << 6, + OTGFS = 1 << 7, + }; + + enum AHB3_dev { + FSMC = 1 << 0, + }; + + enum APB1_dev { + TIM2 = 1 << 0, + TIM3 = 1 << 1, + TIM4 = 1 << 2, + TIM5 = 1 << 3, + TIM6 = 1 << 4, + TIM7 = 1 << 5, + TIM12 = 1 << 6, + TIM13 = 1 << 7, + TIM14 = 1 << 8, + WWDG = 1 << 11, + SPI2 = 1 << 14, + SPI3 = 1 << 15, + USART2 = 1 << 17, + USART3 = 1 << 18, + UART4 = 1 << 19, + UART5 = 1 << 20, + I2C1 = 1 << 21, + I2C2 = 1 << 22, + I2C3 = 1 << 23, + CAN1 = 1 << 25, + CAN2 = 1 << 26, + PWR = 1 << 28, + DAC = 1 << 29, + }; + enum APB2_dev { + TIM1 = 1 << 0, + TIM8 = 1 << 1, + USART1 = 1 << 4, + USART6 = 1 << 5, + ADC = 1 << 8, + SDIO = 1 << 11, + SPI1 = 1 << 12, + SYSCFG = 1 << 14, + TIM9 = 1 << 16, + TIM10 = 1 << 17, + TIM11 = 1 << 18, + }; + #endif + + #if defined(STM32F1) inline void enable(AHB_dev dev) { AHBENR |= dev; } + #elif defined(STM32F4) + inline void enable(AHB1_dev dev) { + AHB1ENR |= dev; + } + inline void enable(AHB2_dev dev) { + AHB2ENR |= dev; + } + + inline void enable(AHB3_dev dev) { + AHB3ENR |= dev; + } + #endif inline void enable(APB1_dev dev) { APB1ENR |= dev; } @@ -115,7 +236,11 @@ struct RCC_t { } }; +#if defined(STM32F1) static RCC_t& RCC = *(RCC_t*)0x40021000; +#elif defined(STM32F4) +static RCC_t& RCC = *(RCC_t*)0x40023800; +#endif struct STK_t { volatile uint32_t CTRL; @@ -132,15 +257,24 @@ struct FLASH_t { volatile uint32_t OPTKEYR; volatile uint32_t SR; volatile uint32_t CR; + #if defined(STM32F1) volatile uint32_t AR; volatile uint32_t RESERVED; volatile uint32_t OBR; volatile uint32_t WRPR; + #elif defined(STM32F4) + volatile uint32_t OPTCR; + #endif }; +#if defined(STM32F1) static FLASH_t& FLASH = *(FLASH_t*)0x40022000; +#elif defined(STM32F4) +static FLASH_t& FLASH = *(FLASH_t*)0x40023c00; +#endif struct GPIO_t { + #if defined(STM32F1) volatile uint32_t CRL; volatile uint32_t CRH; volatile uint32_t IDR; @@ -148,11 +282,35 @@ struct GPIO_t { volatile uint32_t BSRR; volatile uint32_t BRR; volatile uint32_t LCKR; + #elif defined(STM32F4) + volatile uint32_t MODER; + volatile uint32_t OTYPER; + volatile uint32_t OSPEEDER; + volatile uint32_t PUPDR; + volatile uint32_t IDR; + volatile uint32_t ODR; + volatile uint32_t BSRR; + volatile uint32_t LCKR; + volatile uint32_t AFRL; + volatile uint32_t AFRH; + #endif }; +#if defined(STM32F1) static GPIO_t& GPIOA = *(GPIO_t*)0x40010800; static GPIO_t& GPIOB = *(GPIO_t*)0x40010c00; static GPIO_t& GPIOC = *(GPIO_t*)0x40011000; +#elif defined(STM32F4) +static GPIO_t& GPIOA = *(GPIO_t*)0x40020000; +static GPIO_t& GPIOB = *(GPIO_t*)0x40020400; +static GPIO_t& GPIOC = *(GPIO_t*)0x40020800; +static GPIO_t& GPIOD = *(GPIO_t*)0x40020c00; +static GPIO_t& GPIOE = *(GPIO_t*)0x40021000; +static GPIO_t& GPIOF = *(GPIO_t*)0x40021400; +static GPIO_t& GPIOG = *(GPIO_t*)0x40021800; +static GPIO_t& GPIOH = *(GPIO_t*)0x40021c00; +static GPIO_t& GPIOI = *(GPIO_t*)0x40022000; +#endif struct I2C_t { volatile uint32_t CR1; @@ -179,9 +337,15 @@ struct USART_t { volatile uint32_t GTPR; }; +#if defined(STM32F1) static USART_t& USART1 = *(USART_t*)0x40013800; static USART_t& USART2 = *(USART_t*)0x40004400; static USART_t& USART3 = *(USART_t*)0x40004800; +#elif defined(STM32F4) +static USART_t& USART1 = *(USART_t*)0x40011000; +static USART_t& USART2 = *(USART_t*)0x40004400; +static USART_t& USART3 = *(USART_t*)0x40004800; +#endif struct TIM_t { volatile uint32_t CR1; -- cgit v1.2.3