#ifndef STM32_H
#define STM32_H

#include <stdint.h>

struct NVIC_t {
	volatile uint32_t ISER[32];
	volatile uint32_t ICER[32];
	volatile uint32_t ISPR[32];
	volatile uint32_t ICPR[32];
	volatile uint32_t IABR[64];
	volatile uint8_t IPR[2816];
	volatile uint32_t STIR;
};

static NVIC_t& NVIC = *(NVIC_t*)0xe000e100;

struct SCB_t {
	volatile uint32_t CPUID;
	volatile uint32_t ICSR;
	volatile uint32_t VTOR;
	volatile uint32_t AIRCR;
	volatile uint32_t SCR;
	volatile uint32_t CCR;
	volatile uint8_t SHPR[12];
	volatile uint32_t SHCSR;
	volatile uint32_t CFSR;
	volatile uint32_t HFSR;
	volatile uint32_t DFSR;
	volatile uint32_t MMAR;
	volatile uint32_t BFAR;
};

static SCB_t& SCB = *(SCB_t*)0xe000ed00;

struct STK_t {
	volatile uint32_t CTRL;
	volatile uint32_t LOAD;
	volatile uint32_t VAL;
	volatile uint32_t CALIB;
};

static STK_t& STK = *(STK_t*)0xe000e010;

struct TIM_t {
	volatile uint32_t CR1;
	volatile uint32_t CR2;
	volatile uint32_t SMCR;
	volatile uint32_t DIER;
	volatile uint32_t SR;
	volatile uint32_t EGR;
	volatile uint32_t CCMR1;
	volatile uint32_t CCMR2;
	volatile uint32_t CCER;
	volatile uint32_t CNT;
	volatile uint32_t PSC;
	volatile uint32_t ARR;
	volatile uint32_t RCR;
	volatile uint32_t CCR1;
	volatile uint32_t CCR2;
	volatile uint32_t CCR3;
	volatile uint32_t CCR4;
	volatile uint32_t BDTR;
	volatile uint32_t DCR;
	volatile uint32_t DMAR;
};

static TIM_t& TIM1 = *(TIM_t*)0x40012c00;
static TIM_t& TIM2 = *(TIM_t*)0x40000000;
static TIM_t& TIM3 = *(TIM_t*)0x40000400;
static TIM_t& TIM4 = *(TIM_t*)0x40000800;
static TIM_t& TIM5 = *(TIM_t*)0x40000c00;
static TIM_t& TIM6 = *(TIM_t*)0x40001000;
static TIM_t& TIM7 = *(TIM_t*)0x40001400;
static TIM_t& TIM8 = *(TIM_t*)0x40013400;

struct ADC_t {
	volatile uint32_t SR;
	volatile uint32_t CR1;
	volatile uint32_t CR2;
	volatile uint32_t SMPR1;
	volatile uint32_t SMPR2;
	volatile uint32_t JOFR1;
	volatile uint32_t JOFR2;
	volatile uint32_t JOFR3;
	volatile uint32_t JOFR4;
	volatile uint32_t HTR;
	volatile uint32_t LTR;
	volatile uint32_t SQR1;
	volatile uint32_t SQR2;
	volatile uint32_t SQR3;
	volatile uint32_t JSQR;
	volatile uint32_t JDR1;
	volatile uint32_t JDR2;
	volatile uint32_t JDR3;
	volatile uint32_t JDR4;
	volatile uint32_t DR;
};

static ADC_t& ADC1 = *(ADC_t*)0x40012400;
static ADC_t& ADC2 = *(ADC_t*)0x40012800;
static ADC_t& ADC3 = *(ADC_t*)0x40013c00;

struct DMA_t {
	struct CH_t {
		volatile uint32_t CCR;
		volatile uint32_t CNDTR;
		volatile uint32_t CPAR;
		volatile uint32_t CMAR;
		uint32_t _reserved;
	};
	
	volatile uint32_t ISR;
	volatile uint32_t IFCR;
	CH_t CH[7];
};

static DMA_t& DMA1 = *(DMA_t*)0x40020000;
static DMA_t& DMA2 = *(DMA_t*)0x40020400;

#endif