litex: Add UART.

2 files changed, 54 insertions, 0 deletions

diff --git a/uart/SConscript b/uart/SConscript
index dcf6d3e..c37f4aa 100644
--- a/uart/SConscript
+++ b/uart/SConscript
@@ -16,6 +16,15 @@ if 'stm32_uart' in periph:
             'args': [data['offset']],
         })
 
+if 'litex_uart' in periph:
+    headers.append('litex_uart.h')
+    for name, data in periph['litex_uart'].items():
+        instances.append({
+            'type': 'LiteX_UART_t',
+            'name': name,
+            'args': [data['offset']],
+        })
+
 env.Jinja2('uart.h', '../templates/periph_instances.h.j2', headers = headers, instances = instances, aliases = aliases)
 
 Return('sources')
diff --git a/uart/litex_uart.h b/uart/litex_uart.h
new file mode 100644
index 0000000..a1494e6
--- /dev/null
+++ b/uart/litex_uart.h
@@ -0,0 +1,45 @@
+#pragma once
+
+#include <mmio/mmio.h>
+
+struct LiteX_UART_reg_t {
+	volatile uint32_t RXTX;
+	volatile uint32_t TXFULL;
+	volatile uint32_t RXEMPTY;
+	volatile uint32_t EV_STATUS;
+	volatile uint32_t EV_PENDING;
+	volatile uint32_t EV_ENABLE;
+	volatile uint32_t TXEMPTY;
+	volatile uint32_t RXFULL;
+};
+
+class LiteX_UART_t : public mmio_ptr<LiteX_UART_reg_t> {
+    public:
+        using mmio_ptr<LiteX_UART_reg_t>::ptr;
+
+	bool txe() const {
+        return !ptr()->TXFULL;
+	}
+
+	bool rxne() const {
+        return !ptr()->RXEMPTY;
+	}
+
+	uint8_t read() const {
+        return ptr()->RXTX;
+	}
+
+	void write(uint8_t data) const {
+        ptr()->RXTX = data;
+	}
+
+	uint8_t read_blocking() const {
+		while(!rxne());
+		return read();
+	}
+
+	void write_blocking(uint8_t data) const {
+		while(!txe());
+		write(data);
+	}
+};