diff options
author | Vegard Storheil Eriksen <zyp@jvnv.net> | 2016-08-18 23:34:07 +0200 |
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committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2016-08-18 23:34:07 +0200 |
commit | 05dd5f7cdd2d74e304d3b87e5d409cf6f9433020 (patch) | |
tree | 5c0619af7b76a56b5665a7a0a5a0a2615e4fb614 | |
parent | 0417bfe395f23ce9472ee5a2848bc31bc788cb1c (diff) |
Enable CRS.
m--------- | laks | 0 | ||||
-rw-r--r-- | main.cpp | 33 |
2 files changed, 5 insertions, 28 deletions
diff --git a/laks b/laks -Subproject 9c5c5c9243975b20b097dfb65409a3bae31f9d9 +Subproject 6ba3f13d6523d443f91a8dae52855a856101f72 @@ -1,5 +1,6 @@ #include <rcc/flash.h> #include <rcc/rcc.h> +#include <rcc/crs.h> #include <syscfg/syscfg.h> #include <gpio/gpio.h> #include <os/time.h> @@ -458,40 +459,16 @@ class USB_MSC_BBB : public USB_class_driver { USB_MSC_BBB usb_msc_bbb(usb); int main() { - // Configure flash latency. - FLASH.ACR = 1 << 0; - - // Enable HSI16. - RCC.CR |= 1 << 0; // HSI16ON - while(!(RCC.CR & (1 << 2))); // HSI16RDYF - - // Configure PLL. - RCC.CFGR |= (1 << 22) | (1 << 18) | (0 << 16); // PLLDIV = /2, PLLMUL = 4x, PLLSRC = HSI16 - - // Enable PLL. - RCC.CR |= 1 << 24; // PLLON - while(!(RCC.CR & (1 << 25))); // PLLRDY - - // Switch to PLL. - RCC.CFGR |= 3 << 0; // SW = PLL - while((RCC.CFGR & (3 << 2)) != (3 << 2)); // SWS = PLL + rcc_init(); // Initialize system timer. STK.LOAD = 32000000 / 8 / 1000; // 1000 Hz. STK.VAL = 0; STK.CTRL = 0x03; - // Enable VREFINT for HSI48. - RCC.enable(RCC.SYSCFG); - SYSCFG.CFGR3 |= (1 << 13) | (1 << 0); // ENREF_HSI48, EN_VREFINT - while(!(SYSCFG.CFGR3 & (1 << 26))); // REF_HSI48_RDYF - - // Enable HSI48. - RCC.CRRCR |= 1 << 0; // HSI48ON - while(!(RCC.CRRCR & (1 << 1))); // HSI48RDY - - // Select HSI48 for USB. - RCC.CCIPR |= 1 << 26; + // Enable CRS. + RCC.enable(RCC.CRS); + CRS.enable(); RCC.enable(RCC.GPIOA); RCC.enable(RCC.GPIOB); |