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| author | Vegard Storheil Eriksen <zyp@jvnv.net> | 2022-09-10 17:10:09 +0200 |
|---|---|---|
| committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2022-09-10 17:10:09 +0200 |
| commit | 2d75a9be32e2510ff32d331c33178c4625a53054 (patch) | |
| tree | 52375aa3a1be6468184733ab4ea50d232001d9c7 | |
| parent | 59b94427c591e7ec4603b2d9dd6753b1b0927175 (diff) | |
riscv: Add critical section.
| -rw-r--r-- | async/scheduler.h | 2 | ||||
| -rw-r--r-- | interrupt/critical_section.h (renamed from cortex_m/critical_section.h) | 16 | ||||
| -rw-r--r-- | platforms/cortex-m.yaml | 3 | ||||
| -rw-r--r-- | platforms/riscv.yaml | 3 |
4 files changed, 23 insertions, 1 deletions
diff --git a/async/scheduler.h b/async/scheduler.h index bae4890..5c2adaa 100644 --- a/async/scheduler.h +++ b/async/scheduler.h @@ -3,7 +3,7 @@ #include <coroutine> #include <optional> -#include <cortex_m/critical_section.h> +#include <interrupt/critical_section.h> struct schedulable { schedulable* next = nullptr; diff --git a/cortex_m/critical_section.h b/interrupt/critical_section.h index 6b611a8..aec03a5 100644 --- a/cortex_m/critical_section.h +++ b/interrupt/critical_section.h @@ -2,6 +2,7 @@ #include <cstdint> +#ifdef CORTEX_M struct critical_section { uint32_t primask; @@ -19,3 +20,18 @@ struct critical_section { asm volatile("msr primask, %0" :: "r" (primask)); } }; +#endif + +#ifdef RISCV +struct critical_section { + uint32_t mie; + + critical_section() { + asm volatile("csrrw %0, mie, x0" : "=r" (mie)); + } + + ~critical_section() { + asm volatile("csrw mie, %0" :: "r" (mie)); + } +}; +#endif diff --git a/platforms/cortex-m.yaml b/platforms/cortex-m.yaml index ea77615..0a15611 100644 --- a/platforms/cortex-m.yaml +++ b/platforms/cortex-m.yaml @@ -21,6 +21,9 @@ toolchains: - arm-none-eabi + define: + - CORTEX_M + # cortex-m3 - match: cpu: !re cortex-m3 diff --git a/platforms/riscv.yaml b/platforms/riscv.yaml index ec9ecd7..16db64b 100644 --- a/platforms/riscv.yaml +++ b/platforms/riscv.yaml @@ -36,3 +36,6 @@ toolchains: - riscv64-unknown-elf + + define: + - RISCV |