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author | Vegard Storheil Eriksen <zyp@jvnv.net> | 2021-09-16 20:25:24 +0200 |
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committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2021-09-16 20:29:55 +0200 |
commit | 3d4225f210c5b9545a3b4433c983d3a4ffa743a7 (patch) | |
tree | 57233be3907b70d7c8299653fbaa2bcf59f99604 | |
parent | 4d56457b6939d35307880e41bd6a42fe1799e125 (diff) |
rcc: Fix enable register access for devices with multiple registers for the same bus.
-rw-r--r-- | platforms/stm32/wb.yaml | 2 | ||||
-rw-r--r-- | rcc/rcc_enums.h.j2 | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/platforms/stm32/wb.yaml b/platforms/stm32/wb.yaml index 4277085..c41148c 100644 --- a/platforms/stm32/wb.yaml +++ b/platforms/stm32/wb.yaml @@ -64,7 +64,7 @@ 25: FLASH 7: OTGFS - APB1: + APB1_1: 0: TIM2 9: LCD 10: RTCAPB diff --git a/rcc/rcc_enums.h.j2 b/rcc/rcc_enums.h.j2 index 1b0abd0..97e85b9 100644 --- a/rcc/rcc_enums.h.j2 +++ b/rcc/rcc_enums.h.j2 @@ -12,7 +12,7 @@ namespace rcc { template <typename T> void enable(const T& rcc, {{ bus }}_dev dev) { - rcc->{{ bus }}ENR |= dev; + rcc->{{ bus.split('_')[0] }}ENR{{ bus.split('_')[1] if '_' in bus else '' }} |= dev; } {% endfor %} |