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| author | Vegard Storheil Eriksen <zyp@jvnv.net> | 2021-09-15 23:16:11 +0200 |
|---|---|---|
| committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2021-09-15 23:16:11 +0200 |
| commit | 968937d0d937487ab301f017c145889fc0e94692 (patch) | |
| tree | a62e27423fdc515c71624def636b63b12f06cf57 /platforms/riscv.yaml | |
| parent | 9194e871a4590d1118f40ea8dbf1d34e45bc759c (diff) | |
platforms: Add initial RISC-V/GD32V support.
Diffstat (limited to 'platforms/riscv.yaml')
| -rw-r--r-- | platforms/riscv.yaml | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/platforms/riscv.yaml b/platforms/riscv.yaml new file mode 100644 index 0000000..ec9ecd7 --- /dev/null +++ b/platforms/riscv.yaml @@ -0,0 +1,38 @@ +- match: + cpu: rv32imac + + cflags: + - -march=rv32imac + - -mabi=ilp32 + - -msmall-data-limit=0 + + interrupt: + exception: + 0: InstructionMisaligned + 1: InstructionFault + 2: IllegalInstruction + 3: Breakpoint + 4: LoadMisaligned + 5: LoadFault + 6: StoreMisaligned + 7: StoreFault + 8: ECall_U + 9: ECall_S + 11: ECall_M + 12: InstructionPageFault + 13: LoadPageFault + 15: StorePageFault + + internal: + 0: USI + 1: SSI + 3: MSI + 4: UTI + 5: STI + 7: MTI + 8: UEI + 9: SEI + 11: MEI + + toolchains: + - riscv64-unknown-elf |