diff options
| author | Vegard Storheil Eriksen <zyp@jvnv.net> | 2019-03-19 12:56:52 +0100 |
|---|---|---|
| committer | Vegard Storheil Eriksen <v.eriksen@diinef.com> | 2019-03-19 13:02:30 +0100 |
| commit | 6572616a6b4bded686a22377d839cef7506de24d (patch) | |
| tree | f2cc96b9eddafdc6dd29c9ae4f7feb54dda8fa9d /rcc | |
| parent | f1475a7e6cb3077781199981bc3ee74e4ba29b86 (diff) | |
Added STM32F042 support.
Diffstat (limited to 'rcc')
| -rw-r--r-- | rcc/crs.h | 2 | ||||
| -rw-r--r-- | rcc/flash.cpp | 2 | ||||
| -rw-r--r-- | rcc/flash.h | 4 | ||||
| -rw-r--r-- | rcc/rcc.cpp | 10 |
4 files changed, 14 insertions, 4 deletions
@@ -21,7 +21,7 @@ class CRS_t { } }; -#if defined(STM32L0) +#if defined(STM32F0) || defined(STM32L0) static CRS_t CRS(0x40006c00); #endif diff --git a/rcc/flash.cpp b/rcc/flash.cpp index 6469b1c..c20b618 100644 --- a/rcc/flash.cpp +++ b/rcc/flash.cpp @@ -13,7 +13,7 @@ void flash_init() { while(FLASH.ACR != 0x105); - #elif defined(STM32L0) + #elif defined(STM32F0) || defined(STM32L0) // SET flash latency. FLASH.ACR = 1 << 0; diff --git a/rcc/flash.h b/rcc/flash.h index c1f7c1c..789c090 100644 --- a/rcc/flash.h +++ b/rcc/flash.h @@ -4,7 +4,7 @@ #include <stdint.h> struct FLASH_t { - #if defined(STM32F1) || defined(STM32F3) + #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) volatile uint32_t ACR; volatile uint32_t KEYR; volatile uint32_t OPTKEYR; @@ -34,7 +34,7 @@ struct FLASH_t { #endif }; -#if defined(STM32F1) || defined(STM32F3) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) static FLASH_t& FLASH = *(FLASH_t*)0x40022000; #elif defined(STM32F4) static FLASH_t& FLASH = *(FLASH_t*)0x40023c00; diff --git a/rcc/rcc.cpp b/rcc/rcc.cpp index aa9147a..65faf33 100644 --- a/rcc/rcc.cpp +++ b/rcc/rcc.cpp @@ -48,6 +48,16 @@ void rcc_init() { // Set APB2 prescaler to /2. RCC.CFGR |= 4 << 13; + #elif defined(STM32F0) + + // Enable HSI48. + RCC.CR2 |= 1 << 16; // HSI48ON + while(!(RCC.CR2 & (1 << 17))); // HSI48RDY + + // Switch to HSI48. + RCC.CFGR |= 3 << 0; // SW = HSI48 + while((RCC.CFGR & (3 << 2)) != (3 << 2)); // SWS = HSI48 + #elif defined(STM32L0) // Enable HSI16. |