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authorVegard Storheil Eriksen <zyp@jvnv.net>2022-09-10 20:23:18 +0200
committerVegard Storheil Eriksen <zyp@jvnv.net>2022-09-10 20:23:18 +0200
commit37a375c6b7dd83d2ac23069481c566bd9f9a7fd3 (patch)
tree07e050b8aa63627e920f13f4cfe3000b46250917 /uart/litex_uart.h
parentd60be6f83a4519afc0875f28f0959c51edb4fbeb (diff)
litex: Add UART.
Diffstat (limited to 'uart/litex_uart.h')
-rw-r--r--uart/litex_uart.h45
1 files changed, 45 insertions, 0 deletions
diff --git a/uart/litex_uart.h b/uart/litex_uart.h
new file mode 100644
index 0000000..a1494e6
--- /dev/null
+++ b/uart/litex_uart.h
@@ -0,0 +1,45 @@
+#pragma once
+
+#include <mmio/mmio.h>
+
+struct LiteX_UART_reg_t {
+ volatile uint32_t RXTX;
+ volatile uint32_t TXFULL;
+ volatile uint32_t RXEMPTY;
+ volatile uint32_t EV_STATUS;
+ volatile uint32_t EV_PENDING;
+ volatile uint32_t EV_ENABLE;
+ volatile uint32_t TXEMPTY;
+ volatile uint32_t RXFULL;
+};
+
+class LiteX_UART_t : public mmio_ptr<LiteX_UART_reg_t> {
+ public:
+ using mmio_ptr<LiteX_UART_reg_t>::ptr;
+
+ bool txe() const {
+ return !ptr()->TXFULL;
+ }
+
+ bool rxne() const {
+ return !ptr()->RXEMPTY;
+ }
+
+ uint8_t read() const {
+ return ptr()->RXTX;
+ }
+
+ void write(uint8_t data) const {
+ ptr()->RXTX = data;
+ }
+
+ uint8_t read_blocking() const {
+ while(!rxne());
+ return read();
+ }
+
+ void write_blocking(uint8_t data) const {
+ while(!txe());
+ write(data);
+ }
+};