diff options
Diffstat (limited to 'rcc')
| -rw-r--r-- | rcc/flash.h | 26 | ||||
| -rw-r--r-- | rcc/rcc.h | 154 |
2 files changed, 179 insertions, 1 deletions
diff --git a/rcc/flash.h b/rcc/flash.h index c1f7c1c..97875c6 100644 --- a/rcc/flash.h +++ b/rcc/flash.h @@ -31,6 +31,30 @@ struct FLASH_t { volatile uint32_t SR; volatile uint32_t OPTR; volatile uint32_t WRPROT; + #elif defined(STM32WB) + volatile uint32_t ACR; + uint32_t _reserved; + volatile uint32_t KEYR; + volatile uint32_t OPTKEYR; + volatile uint32_t SR; + volatile uint32_t CR; + volatile uint32_t ECCR; + uint32_t _reserved_1; + volatile uint32_t OPTR; + volatile uint32_t PCROP1ASR; + volatile uint32_t PCROP1AER; + volatile uint32_t WRP1AR; + volatile uint32_t WRP1BR; + volatile uint32_t PCROP1BSR; + volatile uint32_t PCROP1BER; + volatile uint32_t IPCCBR; + uint32_t _reserved_2[7]; + volatile uint32_t C2ACR; + volatile uint32_t C2SR; + volatile uint32_t C2CR; + uint32_t _reserved_3[6]; + volatile uint32_t SFR; + volatile uint32_t SRRVR; #endif }; @@ -40,6 +64,8 @@ static FLASH_t& FLASH = *(FLASH_t*)0x40022000; static FLASH_t& FLASH = *(FLASH_t*)0x40023c00; #elif defined(STM32L0) static FLASH_t& FLASH = *(FLASH_t*)0x40022000; +#elif defined(STM32WB) +static FLASH_t& FLASH = *(FLASH_t*)0x58004000; #endif void flash_init(); @@ -86,6 +86,67 @@ struct RCC_t { volatile uint32_t APB1SMENR; volatile uint32_t CCIPR; volatile uint32_t CSR; + #elif defined(STM32WB) + volatile uint32_t CR; + volatile uint32_t ICSCR; + volatile uint32_t CFGR; + volatile uint32_t PLLCFGR; + volatile uint32_t PLLSAI1CFGR; + uint32_t _reserved; + volatile uint32_t CIER; + volatile uint32_t CIFR; + volatile uint32_t CICR; + volatile uint32_t SMPSCR; + volatile uint32_t AHB1RSTR; + volatile uint32_t AHB2RSTR; + volatile uint32_t AHB3RSTR; + uint32_t _reserved_1; + volatile uint32_t APB1RSTR1; + volatile uint32_t APB1RSTR2; + volatile uint32_t APB2RSTR; + volatile uint32_t APB3RSTR; + volatile uint32_t AHB1ENR; + volatile uint32_t AHB2ENR; + volatile uint32_t AHB3ENR; + uint32_t _reserved_2; + volatile uint32_t APB1ENR1; + volatile uint32_t APB1ENR2; + volatile uint32_t APB2ENR; + uint32_t _reserved_3; + volatile uint32_t AHB1SMENR; + volatile uint32_t AHB2SMENR; + volatile uint32_t AHB3SMENR; + uint32_t _reserved_4; + volatile uint32_t APB1SMENR1; + volatile uint32_t APB1SMENR2; + volatile uint32_t APB2SMENR; + uint32_t _reserved_5; + volatile uint32_t CCIPR; + uint32_t _reserved_6; + volatile uint32_t BDCR; + volatile uint32_t CSR; + volatile uint32_t CRRCR; + volatile uint32_t HSECR; + uint32_t _reserved_7[26]; + volatile uint32_t EXTCFGR; + uint32_t _reserved_8[15]; + // TODO: more + volatile uint32_t C2AHB1ENR; + volatile uint32_t C2AHB2ENR; + volatile uint32_t C2AHB3ENR; + uint32_t _reserved_9; + volatile uint32_t C2APB1ENR1; + volatile uint32_t C2APB1ENR2; + volatile uint32_t C2APB2ENR; + volatile uint32_t C2APB3ENR; + volatile uint32_t C2AHB1SMENR; + volatile uint32_t C2AHB2SMENR; + volatile uint32_t C2AHB3SMENR; + uint32_t _reserved_10; + volatile uint32_t C2APB1SMENR1; + volatile uint32_t C2APB1SMENR2; + volatile uint32_t C2APB2SMENR; + volatile uint32_t C2APB3SMENR; #endif #if defined(STM32F1) @@ -311,12 +372,76 @@ struct RCC_t { GPIOD = 1 << 3, GPIOH = 1 << 7, }; + #elif defined(STM32WB) + enum AHB1_dev { + DMA1 = 1 << 0, + DMA2 = 1 << 1, + DMAMUX1 = 1 << 2, + CRC = 1 << 12, + TSC = 1 << 16, + }; + + enum AHB2_dev { + GPIOA = 1 << 0, + GPIOB = 1 << 1, + GPIOC = 1 << 2, + GPIOD = 1 << 3, + GPIOE = 1 << 4, + GPIOH = 1 << 7, + ADC = 1 << 13, + AES1 = 1 << 16, + }; + + enum AHB3_dev { + QUADSPI = 1 << 8, + PKA = 1 << 16, + AES2 = 1 << 17, + RNG = 1 << 18, + HSEM = 1 << 19, + IPCC = 1 << 20, + FLASH = 1 << 25, + }; + + enum APB1_dev { + TIM2 = 1 << 0, + LCD = 1 << 9, + RTCAPB = 1 << 10, + WWDG = 1 << 11, + SPI2 = 1 << 14, + I2C1 = 1 << 21, + I2C3 = 1 << 23, + CRS = 1 << 24, + USB = 1 << 26, + LPTIM1 = 1 << 31, + }; + + enum APB1_2_dev { + LPUART1 = 1 << 0, + LPTIM2 = 1 << 5, + }; + + enum APB2_dev { + TIM1 = 1 << 11, + SPI1 = 1 << 12, + USART1 = 1 << 14, + TIM16 = 1 << 17, + TIM17 = 1 << 18, + SAI1 = 1 << 21, + }; #endif #if defined(STM32F1) || defined(STM32F3) || defined(STM32L0) inline void enable(AHB_dev dev) { AHBENR |= dev; } + + inline void enable(APB1_dev dev) { + APB1ENR |= dev; + } + + inline void enable(APB2_dev dev) { + APB2ENR |= dev; + } #elif defined(STM32F4) inline void enable(AHB1_dev dev) { AHB1ENR |= dev; @@ -329,7 +454,7 @@ struct RCC_t { inline void enable(AHB3_dev dev) { AHB3ENR |= dev; } - #endif + inline void enable(APB1_dev dev) { APB1ENR |= dev; } @@ -337,6 +462,31 @@ struct RCC_t { inline void enable(APB2_dev dev) { APB2ENR |= dev; } + #elif defined(STM32WB) + inline void enable(AHB1_dev dev) { + AHB1ENR |= dev; + } + + inline void enable(AHB2_dev dev) { + AHB2ENR |= dev; + } + + inline void enable(AHB3_dev dev) { + AHB3ENR |= dev; + } + + inline void enable(APB1_dev dev) { + APB1ENR1 |= dev; + } + + inline void enable(APB1_2_dev dev) { + APB1ENR2 |= dev; + } + + inline void enable(APB2_dev dev) { + APB2ENR |= dev; + } + #endif #if defined(STM32L0) inline void enable(IOP_dev dev) { IOPENR |= dev; @@ -348,6 +498,8 @@ struct RCC_t { static RCC_t& RCC = *(RCC_t*)0x40021000; #elif defined(STM32F4) static RCC_t& RCC = *(RCC_t*)0x40023800; +#elif defined(STM32WB) +static RCC_t& RCC = *(RCC_t*)0x58000000; #endif void rcc_init(); |