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/*
* This file is auto-generated from a template!
* You should reconsider editing!
*/
MEMORY {
{% for name, m in mem.items() %}
{{ name }} ({{ 'rx' if name == 'flash' else 'rwx' }}) : org = {{ m.origin | hex }}, len = {{ m.size | size_prefix }}
{% endfor %}
}
SECTIONS {
. = 0;
.vectors : ALIGN(16) SUBALIGN(16) {
KEEP(*(.vectors))
} > flash
.init_array : ALIGN(4) SUBALIGN(4) {
PROVIDE(_init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(_init_array_end = .);
} > flash
.fini_array : ALIGN(4) SUBALIGN(4) {
PROVIDE(_fini_array_start = .);
KEEP(*(.fini_array))
KEEP(*(SORT(.fini_array.*)))
PROVIDE(_fini_array_end = .);
} > flash
.text : ALIGN(4) SUBALIGN(4) {
*(.text.startup.*)
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.srodata)
*(.srodata.*)
*(.glue_7t)
*(.glue_7)
*(.gcc*)
} > flash
.bootinfo : ALIGN(4) SUBALIGN(4) {
*(.bootinfo)
} > ram
. = ALIGN(4);
.data : ALIGN(4) SUBALIGN(4) {
PROVIDE(_data_start = .);
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.ramtext)
PROVIDE(_data_end = .);
} > ram AT > flash
.bss : {
PROVIDE(_bss_start = .);
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
*(COMMON)
PROVIDE(_bss_end = .);
} > ram
PROVIDE(_ram_end = ORIGIN(ram) + LENGTH(ram));
PROVIDE(_data_rom = LOADADDR(.data));
}
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