summaryrefslogtreecommitdiff
path: root/rcc/rcc.cpp
blob: c5eab44a73b2cfea44bf83199940c964e6f601f5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
#include "rcc.h"
#include "flash.h"

void rcc_init() {
	// Initialize flash.
	flash_init();
	
	#if defined(STM32F1) || defined(STM32F3)
	
	// Enable HSE.
	RCC.CR |= 0x10000;
	while(!(RCC.CR & 0x20000));
	
	// Configure and enable PLL.
	RCC.CFGR = (4 << 18) | (1 << 16); // PLLMUL = x6, PLLSRC = HSE
	RCC.CR |= 0x1000000;
	while(!(RCC.CR & 0x2000000));
	
	// Switch to PLL.
	RCC.CFGR |= 0x2;
	while(!(RCC.CFGR & 0x8));
	
	// Set APB1 prescaler to /2.
	RCC.CFGR |= 0x400;
	
	// Set ADCCLK prescaler to /6.
	RCC.CFGR |= 0x8000;
	
	#elif defined(STM32F4)
	
	// Enable HSE.
	RCC.CR |= 0x10000;
	while(!(RCC.CR & 0x20000));
	
	// Configure and enable PLL.
	RCC.PLLCFGR = 0x20400000 | (7 << 24) | (2 * 168 << 6) | 8;
	RCC.CR |= 0x1000000;
	while(!(RCC.CR & 0x2000000));
	
	// Switch to PLL.
	RCC.CFGR |= 0x2;
	while(!(RCC.CFGR & 0x8));
	
	// Set APB1 prescaler to /4.
	RCC.CFGR |= 5 << 10;
	
	// Set APB2 prescaler to /2.
	RCC.CFGR |= 4 << 13;
	
	#endif
}