summaryrefslogtreecommitdiff
path: root/rcc
AgeCommit message (Collapse)AuthorFilesLines
2022-04-16stm32_flash: l4/wb/g4 fix reserved gapsKarl Palsson1-4/+13
l4 and g4 are the same, g4 just has some extra registers, and the first section is the same for wb as well, all of them had missing reserved registers.
2022-04-16stm32g4: initial platform supportKarl Palsson1-0/+23
Have some demo code using lptim, lpuart, exti and rtc mostly working. It glitches into undefined exceptions, so it's a little concerning, but... it's all cross checked against RM0440_rev7, so it's pretty good. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-04-16FIXME: platforms: stm32l4: fix all rcc enables, add lptimKarl Palsson1-0/+44
FIXME: LPTIM should be split out, rcc should squish to earlier, as early as we can with other rcc fixes,post the last dev_v2 merge.
2022-04-16rcc: add "disable" methods for low powerKarl Palsson2-0/+10
Some people might like to turn peripherals back off again. We have all the machinery in place, so make it easy for them. Signed-off-by: Karl Palsson <karlp@etactica.com>
2022-04-16stm32f7: Add more peripherals.Vegard Storheil Eriksen3-2/+5
2022-01-26stm32l1: initial support, incompleteKarl Palsson1-0/+18
2022-01-26stm32_syscfg: convert to modern.Karl Palsson1-19/+0
Includes the f4, l0 and wb. f4 renames MEMRM to MEMRMP to be both consistent with other parts and consistent with ref man. Retested on the WB, but l0 and f4 code was simply moved. For yaml files, given how varied syscfg is, we default to using the family name as the type, but still allow overriding via explicit type in the yaml file if desired. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32l4: add basic platform fileKarl Palsson1-0/+15
While checking STM32WB, this was easy enough to just transcribe while working. Untested on real hardware. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26rcc: stm32wb: add remaining regs and max speed helperKarl Palsson2-10/+51
Max speed on WB is 32MHz HSE to 64MHz PLL. Must ensure that CPU2 doesn't exceed 32MHz though. Adds the remaining RCC registers and bits as well. Most of these are not useful, as you can't really/meaningfully deliver software to CPU2, but some of them are used/required by the ST provided WPAN middleware. Signed-off-by: Karl Palsson <karlp@etactica.com> Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2022-01-26stm32_rcc: allow aliases for enables.Karl Palsson1-1/+1
By flipping the name/number definition, we can define aliases such as ADC and ADC1, or FMC/FSMC for the same bits, making it easier to have code that both matches reference manuals, and also code that matches between lines. runtime tested on WB, compile tested on F3. Signed-off-by: Karl Palsson <karlp@etactica.com>
2022-01-26flash: convert to new styleKarl Palsson4-26/+46
2022-01-20adc: stm32f3: expand and verifyKarl Palsson1-3/+7
Working with dma and timers. This preserves the somewhat dubious decision that ADC clock for F1 and F3 should be 12Mhz. It can always be overridden later.
2022-01-20platforms: stm32f3: make functionalKarl Palsson1-5/+5
Sufficient for blinking leds. Not much else tested yet. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16flash: stm32wb: oldstyle: add register map and basic initKarl Palsson2-0/+31
Flash hasn't yet been ported to new style. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2021-09-16rcc: Fix enable register access for devices with multiple registers for the ↵Vegard Storheil Eriksen1-1/+1
same bus.
2021-09-16platforms: add stm32wbKarl Palsson1-0/+46
Basic RCC and memory map support. Signed-off-by: Karl Palsson <karlp@etactica.com>
2021-09-16rcc: include a static file with function prototypesKarl Palsson2-0/+7
Authors modifying rcc.cpp should add their protos here as desired. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2021-09-16generators: clearly mark generated filesKarl Palsson1-0/+2
This makes it easier for end users to see where files have come from. Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2021-09-15platforms: Improve STM32F42x support.Vegard Storheil Eriksen1-2/+2
2021-01-26rcc: Generate enables from platform spec.Vegard Storheil Eriksen5-472/+213
2019-03-19Added STM32F042 support.Vegard Storheil Eriksen4-4/+14
2019-03-19Added STM32F0 support.Vegard Storheil Eriksen1-4/+72
2017-05-14STM32F4: Added rcc_init() overload with sysclk argument.Vegard Storheil Eriksen2-0/+44
2016-08-19STM32L0: Fixed typo in FLASH_PEKEYR.Vegard Storheil Eriksen1-1/+1
2016-08-18STM32L0: Add CRS definition.Vegard Storheil Eriksen1-0/+30
2016-08-18Add STM32L0 to rcc_init().Vegard Storheil Eriksen2-0/+35
2016-08-18Added STM32L0 support.Vegard Storheil Eriksen2-3/+91
2012-12-29Fixed F1 RCC bug.Vegard Storheil Eriksen1-1/+1
2012-12-10Added ethernet and syscfg register definitions.Vegard Storheil Eriksen2-0/+22
2012-11-19Added support for F3.Vegard Storheil Eriksen4-6/+69
2012-10-09Add OTGHSULPI clock gate definition.Vegard Storheil Eriksen1-14/+15
2012-09-05Renamed RCC.IOPx to RCC.GPIOx for F1.Vegard Storheil Eriksen1-7/+7
2012-08-07Initial import.Vegard Storheil Eriksen4-0/+315
Most sources are split off from suzumebachi project revision 2fc77d2 as is with some path changes. New build rules introduced.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 23:28:28 +0100