diff options
| author | Vegard Storheil Eriksen <zyp@jvnv.net> | 2011-07-02 22:18:46 +0200 |
|---|---|---|
| committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2011-07-02 22:18:46 +0200 |
| commit | 3e8f4833fb1bd26ffd5a18bbdc392e9899b7bbf5 (patch) | |
| tree | 16f33ffa31aa59eb35f0d509b0b9284742cf2c88 | |
| parent | 9b22cfb2aad32aeb5c0e878e7b72b1590296cf7d (diff) | |
Added timer registers.
| -rw-r--r-- | stm32.h | 32 |
1 files changed, 32 insertions, 0 deletions
@@ -174,4 +174,36 @@ static USART_t& USART1 = *(USART_t*)0x40013800; static USART_t& USART2 = *(USART_t*)0x40004400; static USART_t& USART3 = *(USART_t*)0x40004800; +struct TIM_t { + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t SMCR; + volatile uint32_t DIER; + volatile uint32_t SR; + volatile uint32_t EGR; + volatile uint32_t CCMR1; + volatile uint32_t CCMR2; + volatile uint32_t CCER; + volatile uint32_t CNT; + volatile uint32_t PSC; + volatile uint32_t ARR; + volatile uint32_t RCR; + volatile uint32_t CCR1; + volatile uint32_t CCR2; + volatile uint32_t CCR3; + volatile uint32_t CCR4; + volatile uint32_t BDTR; + volatile uint32_t DCR; + volatile uint32_t DMAR; +}; + +static TIM_t& TIM1 = *(TIM_t*)0x40012c00; +static TIM_t& TIM2 = *(TIM_t*)0x40000000; +static TIM_t& TIM3 = *(TIM_t*)0x40000400; +static TIM_t& TIM4 = *(TIM_t*)0x40000800; +static TIM_t& TIM5 = *(TIM_t*)0x40000c00; +static TIM_t& TIM6 = *(TIM_t*)0x40001000; +static TIM_t& TIM7 = *(TIM_t*)0x40001400; +static TIM_t& TIM8 = *(TIM_t*)0x40013400; + #endif |