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authorVegard Storheil Eriksen <zyp@jvnv.net>2011-07-02 13:25:21 +0200
committerVegard Storheil Eriksen <zyp@jvnv.net>2011-07-02 13:25:21 +0200
commit8e41564e1093873432e95fffb3787f8b78f8f1b5 (patch)
tree47795a706ad5be6caace49f5372164da6de443cb
parenta6dc2b0ad2bf5efd2c9f49754ff7057f5c24a929 (diff)
Added NVIC and SCB registers.
-rw-r--r--stm32.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/stm32.h b/stm32.h
index da84bfc..9ed56d6 100644
--- a/stm32.h
+++ b/stm32.h
@@ -3,6 +3,36 @@
#include <stdint.h>
+struct NVIC_t {
+ volatile uint32_t ISER[32];
+ volatile uint32_t ICER[32];
+ volatile uint32_t ISPR[32];
+ volatile uint32_t ICPR[32];
+ volatile uint32_t IABR[64];
+ volatile uint8_t IPR[2816];
+ volatile uint32_t STIR;
+};
+
+static NVIC_t& NVIC = *(NVIC_t*)0xe000e100;
+
+struct SCB_t {
+ volatile uint32_t CPUID;
+ volatile uint32_t ICSR;
+ volatile uint32_t VTOR;
+ volatile uint32_t AIRCR;
+ volatile uint32_t SCR;
+ volatile uint32_t CCR;
+ volatile uint8_t SHPR[12];
+ volatile uint32_t SHCSR;
+ volatile uint32_t CFSR;
+ volatile uint32_t HFSR;
+ volatile uint32_t DFSR;
+ volatile uint32_t MMAR;
+ volatile uint32_t BFAR;
+};
+
+static SCB_t& SCB = *(SCB_t*)0xe000ed00;
+
struct RCC_t {
volatile uint32_t CR;
volatile uint32_t CFGR;