diff options
author | Vegard Storheil Eriksen <zyp@jvnv.net> | 2013-03-06 16:57:25 +0100 |
---|---|---|
committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2013-03-06 16:57:25 +0100 |
commit | d61154c544a697d98e4b7719f798b0cd8ff8381a (patch) | |
tree | accbeff1cd02ff326ec193679be904fc65719b40 | |
parent | 9926e0ac414371bcaea5302a50715bd631267fcf (diff) |
Run SPI at 5.25 MHz.
-rw-r--r-- | drivers/l3gd20.h | 2 | ||||
-rw-r--r-- | main.cpp | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/l3gd20.h b/drivers/l3gd20.h index f305de1..1d2ac88 100644 --- a/drivers/l3gd20.h +++ b/drivers/l3gd20.h @@ -17,7 +17,7 @@ class L3GD20 { L3GD20(Pin& cs_pin, SPI_t& spi_bus) : cs(cs_pin), spi(spi_bus) {} void init() { - spi.reg.CR1 = 0x37f; + spi.reg.CR1 = (1 << 9) | (1 << 8) | (1 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | (1 << 0); // SSM, SSI, SPE, 84/16MHz, MSTR, CPOL, CPHA cs.off(); spi.transfer_byte(0x40 | 0x20); spi.transfer_byte(0xff); @@ -247,7 +247,7 @@ int main() { cs_pressure.on(); cs_pressure.set_mode(Pin::Output); - SPI1.reg.CR1 = 0x37f; + SPI1.reg.CR1 = (1 << 9) | (1 << 8) | (1 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | (1 << 0); // SSM, SSI, SPE, 84/16MHz, MSTR, CPOL, CPHA Time::sleep(1000); |