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authorVegard Storheil Eriksen <zyp@jvnv.net>2011-12-03 19:12:02 +0100
committerVegard Storheil Eriksen <zyp@jvnv.net>2011-12-03 19:12:02 +0100
commitf886d12a39d3d9c293eb87aa239165f1f52cd9f0 (patch)
tree6e829bce2b0e521b742769481fe029c0cec5348c
parent89225b336c715d3b11bcc0d5b4ef0b80c2bd28f9 (diff)
hal/rcc.cpp
-rw-r--r--hal/rcc.cpp32
1 files changed, 31 insertions, 1 deletions
diff --git a/hal/rcc.cpp b/hal/rcc.cpp
index e3ae38d..5a82d62 100644
--- a/hal/rcc.cpp
+++ b/hal/rcc.cpp
@@ -2,6 +2,8 @@
#include "stm32.h"
void rcc_init() {
+ #if defined(STM32F1)
+
// Set flash latency.
FLASH.ACR = 0x12;
@@ -12,7 +14,7 @@ void rcc_init() {
// Configure and enable PLL.
RCC.CFGR = 0x1d0000;
RCC.CR |= 0x1000000;
- while(RCC.CR & 0x2000000);
+ while(!(RCC.CR & 0x2000000));
// Switch to PLL.
RCC.CFGR |= 0x2;
@@ -23,4 +25,32 @@ void rcc_init() {
// Set ADCCLK prescaler to /6.
RCC.CFGR |= 0x8000;
+
+ #elif defined(STM32F4)
+
+ // Set flash latency.
+ FLASH.ACR = 0x105;
+
+ while(FLASH.ACR != 0x105);
+
+ // Enable HSE.
+ RCC.CR |= 0x10000;
+ while(!(RCC.CR & 0x20000));
+
+ // Configure and enable PLL.
+ RCC.PLLCFGR = 0x20400000 | (7 << 24) | (2 * 168 << 6) | 8;
+ RCC.CR |= 0x1000000;
+ while(!(RCC.CR & 0x2000000));
+
+ // Switch to PLL.
+ RCC.CFGR |= 0x2;
+ while(!(RCC.CFGR & 0x8));
+
+ // Set APB1 prescaler to /4.
+ RCC.CFGR |= 5 << 10;
+
+ // Set APB2 prescaler to /2.
+ RCC.CFGR |= 4 << 13;
+
+ #endif
}