diff options
| author | Vegard Storheil Eriksen <zyp@jvnv.net> | 2012-07-29 13:32:37 +0200 |
|---|---|---|
| committer | Vegard Storheil Eriksen <zyp@jvnv.net> | 2012-07-29 13:32:37 +0200 |
| commit | 2fc77d271db27ecb140191c2dfafdba835962ffb (patch) | |
| tree | 4e3c07dc84116c4a05f18442dbb0fef1e56e2e22 /hal | |
| parent | 7099e9c67abe16f78d62f53ddaa8c75f015d098a (diff) | |
Ported ppmsum driver to r3 board.
Diffstat (limited to 'hal')
| -rw-r--r-- | hal/stm32.h | 32 | ||||
| -rw-r--r-- | hal/timer.h | 40 |
2 files changed, 40 insertions, 32 deletions
diff --git a/hal/stm32.h b/hal/stm32.h index 6c7a04b..68848d8 100644 --- a/hal/stm32.h +++ b/hal/stm32.h @@ -42,38 +42,6 @@ struct STK_t { static STK_t& STK = *(STK_t*)0xe000e010; -struct TIM_t { - volatile uint32_t CR1; - volatile uint32_t CR2; - volatile uint32_t SMCR; - volatile uint32_t DIER; - volatile uint32_t SR; - volatile uint32_t EGR; - volatile uint32_t CCMR1; - volatile uint32_t CCMR2; - volatile uint32_t CCER; - volatile uint32_t CNT; - volatile uint32_t PSC; - volatile uint32_t ARR; - volatile uint32_t RCR; - volatile uint32_t CCR1; - volatile uint32_t CCR2; - volatile uint32_t CCR3; - volatile uint32_t CCR4; - volatile uint32_t BDTR; - volatile uint32_t DCR; - volatile uint32_t DMAR; -}; - -static TIM_t& TIM1 = *(TIM_t*)0x40012c00; -static TIM_t& TIM2 = *(TIM_t*)0x40000000; -static TIM_t& TIM3 = *(TIM_t*)0x40000400; -static TIM_t& TIM4 = *(TIM_t*)0x40000800; -static TIM_t& TIM5 = *(TIM_t*)0x40000c00; -static TIM_t& TIM6 = *(TIM_t*)0x40001000; -static TIM_t& TIM7 = *(TIM_t*)0x40001400; -static TIM_t& TIM8 = *(TIM_t*)0x40013400; - struct ADC_t { volatile uint32_t SR; volatile uint32_t CR1; diff --git a/hal/timer.h b/hal/timer.h new file mode 100644 index 0000000..f9305de --- /dev/null +++ b/hal/timer.h @@ -0,0 +1,40 @@ +#ifndef TIMER_H +#define TIMER_H + +struct TIM_t { + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t SMCR; + volatile uint32_t DIER; + volatile uint32_t SR; + volatile uint32_t EGR; + volatile uint32_t CCMR1; + volatile uint32_t CCMR2; + volatile uint32_t CCER; + volatile uint32_t CNT; + volatile uint32_t PSC; + volatile uint32_t ARR; + volatile uint32_t RCR; + volatile uint32_t CCR1; + volatile uint32_t CCR2; + volatile uint32_t CCR3; + volatile uint32_t CCR4; + volatile uint32_t BDTR; + volatile uint32_t DCR; + volatile uint32_t DMAR; +}; + +#if defined(STM32F1) +static TIM_t& TIM1 = *(TIM_t*)0x40012c00; +static TIM_t& TIM2 = *(TIM_t*)0x40000000; +static TIM_t& TIM3 = *(TIM_t*)0x40000400; +static TIM_t& TIM4 = *(TIM_t*)0x40000800; +static TIM_t& TIM5 = *(TIM_t*)0x40000c00; +static TIM_t& TIM6 = *(TIM_t*)0x40001000; +static TIM_t& TIM7 = *(TIM_t*)0x40001400; +static TIM_t& TIM8 = *(TIM_t*)0x40013400; +#elif defined(STM32F4) +static TIM_t& TIM2 = *(TIM_t*)0x40000000; +#endif + +#endif |